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author | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2014-03-01 17:51:00 +0000 |
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committer | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2014-03-01 17:51:00 +0000 |
commit | e1f5cd3002456d8a7d091ca7e4b9a6d259745796 (patch) | |
tree | e66404adf5c8e3a4b4db2885dbf7ce7ff4cfffff /lib/Target/Sparc/SparcInstrInfo.td | |
parent | 71e50f0afd94be865ce796728740daa5ca916849 (diff) | |
download | llvm-e1f5cd3002456d8a7d091ca7e4b9a6d259745796.tar.gz llvm-e1f5cd3002456d8a7d091ca7e4b9a6d259745796.tar.bz2 llvm-e1f5cd3002456d8a7d091ca7e4b9a6d259745796.tar.xz |
[Sparc] Add missing ALU instruction patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202597 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Sparc/SparcInstrInfo.td')
-rw-r--r-- | lib/Target/Sparc/SparcInstrInfo.td | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index c990741b6b..d855503870 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -466,6 +466,15 @@ def XNORri : F3_2<2, 0b000111, (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13), "xnor $rs1, $simm13, $rd", []>; +let Defs = [ICC] in { + defm ANDCC : F3_12np<"andcc", 0b010001>; + defm ANDNCC : F3_12np<"andncc", 0b010101>; + defm ORCC : F3_12np<"orcc", 0b010010>; + defm ORNCC : F3_12np<"orncc", 0b010110>; + defm XORCC : F3_12np<"xorcc", 0b010011>; + defm XNORCC : F3_12np<"xnorcc", 0b010111>; +} + // Section B.12 - Shift Instructions, p. 107 defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, simm13Op>; defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, simm13Op>; @@ -484,6 +493,9 @@ let Predicates = [Is32Bit], isCodeGenOnly = 1 in let Defs = [ICC] in defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, simm13Op>; +let Uses = [ICC] in + defm ADDC : F3_12np<"addx", 0b001000>; + let Uses = [ICC], Defs = [ICC] in defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>; @@ -495,6 +507,9 @@ let Uses = [ICC], Defs = [ICC] in let Defs = [ICC] in defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, simm13Op>; +let Uses = [ICC] in + defm SUBC : F3_12np <"subx", 0b001100>; + let Defs = [ICC], rd = 0 in { def CMPrr : F3_1<2, 0b010100, (outs), (ins IntRegs:$rs1, IntRegs:$rs2), @@ -512,12 +527,22 @@ let Defs = [Y] in { defm SMUL : F3_12 <"smul", 0b001011, mul, IntRegs, i32, simm13Op>; } +let Defs = [Y, ICC] in { + defm UMULCC : F3_12np<"umulcc", 0b011010>; + defm SMULCC : F3_12np<"smulcc", 0b011011>; +} + // Section B.19 - Divide Instructions, p. 115 let Defs = [Y] in { defm UDIV : F3_12np<"udiv", 0b001110>; defm SDIV : F3_12np<"sdiv", 0b001111>; } +let Defs = [Y, ICC] in { + defm UDIVCC : F3_12np<"udivcc", 0b011110>; + defm SDIVCC : F3_12np<"sdivcc", 0b011111>; +} + // Section B.20 - SAVE and RESTORE, p. 117 defm SAVE : F3_12np<"save" , 0b111100>; defm RESTORE : F3_12np<"restore", 0b111101>; @@ -972,6 +997,16 @@ let Predicates = [HasV9], Constraints = "$swap = $rd" in [(set i32:$rd, (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>; +let Defs = [ICC] in { +defm TADDCC : F3_12np<"taddcc", 0b100000>; +defm TSUBCC : F3_12np<"tsubcc", 0b100001>; + +let hasSideEffects = 1 in { + defm TADDCCTV : F3_12np<"taddcctv", 0b100010>; + defm TSUBCCTV : F3_12np<"tsubcctv", 0b100011>; +} +} + //===----------------------------------------------------------------------===// // Non-Instruction Patterns //===----------------------------------------------------------------------===// |