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author | Evan Cheng <evan.cheng@apple.com> | 2007-07-21 00:34:19 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2007-07-21 00:34:19 +0000 |
commit | ffbaccae029ac238972e3814967260f029b6058a (patch) | |
tree | 0a3938c96b46a1c4b638963673c52135fd80cb3c /lib/Target/Sparc/SparcInstrInfo.td | |
parent | c674a924d4ed62e857bf788d7e0c76c89239b903 (diff) | |
download | llvm-ffbaccae029ac238972e3814967260f029b6058a.tar.gz llvm-ffbaccae029ac238972e3814967260f029b6058a.tar.bz2 llvm-ffbaccae029ac238972e3814967260f029b6058a.tar.xz |
No more noResults.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40132 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Sparc/SparcInstrInfo.td')
-rw-r--r-- | lib/Target/Sparc/SparcInstrInfo.td | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index 7a32f07bc9..ff2ed87170 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -267,7 +267,7 @@ let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. // Section A.3 - Synthetic Instructions, p. 85 // special cases of JMPL: -let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in { +let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in { let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in def RETL: F3_2<2, 0b111000, (outs), (ins), "retl", [(retflag)]>; } @@ -464,7 +464,6 @@ class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> let isBranch = 1; let isTerminator = 1; let hasDelaySlot = 1; - let noResults = 1; } let isBarrier = 1 in @@ -486,7 +485,6 @@ class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> let isBranch = 1; let isTerminator = 1; let hasDelaySlot = 1; - let noResults = 1; } // FIXME: the encoding for the JIT should look at the condition field. @@ -498,7 +496,7 @@ def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc), // Section B.24 - Call and Link Instruction, p. 125 // This is the only Format 1 instruction let Uses = [O0, O1, O2, O3, O4, O5], - hasDelaySlot = 1, isCall = 1, noResults = 1, + hasDelaySlot = 1, isCall = 1, Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in { def CALL : InstSP<(outs), (ins calltarget:$dst), |