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author | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2014-03-09 23:32:07 +0000 |
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committer | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2014-03-09 23:32:07 +0000 |
commit | 08da01c74136c221ec0cfcb00db8552ce926f54c (patch) | |
tree | 1a86d4e18a3ed065bd3cef8ddae8a74f09f7676b /lib/Target/Sparc | |
parent | f749c23912418547085d3b43964163a55d8a2e82 (diff) | |
download | llvm-08da01c74136c221ec0cfcb00db8552ce926f54c.tar.gz llvm-08da01c74136c221ec0cfcb00db8552ce926f54c.tar.bz2 llvm-08da01c74136c221ec0cfcb00db8552ce926f54c.tar.xz |
[Sparc] Add support for decoding 'swap' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203424 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Sparc')
-rw-r--r-- | lib/Target/Sparc/Disassembler/SparcDisassembler.cpp | 36 | ||||
-rw-r--r-- | lib/Target/Sparc/SparcInstrInfo.td | 2 |
2 files changed, 37 insertions, 1 deletions
diff --git a/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp b/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp index df2d3798a2..5cd99d6bfe 100644 --- a/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp +++ b/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp @@ -211,6 +211,8 @@ static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address, + const void *Decoder); #include "SparcGenDisassemblerTables.inc" @@ -445,3 +447,37 @@ static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, } return MCDisassembler::Success; } + +static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address, + const void *Decoder) { + + unsigned rd = fieldFromInstruction(insn, 25, 5); + unsigned rs1 = fieldFromInstruction(insn, 14, 5); + unsigned isImm = fieldFromInstruction(insn, 13, 1); + unsigned rs2 = 0; + unsigned simm13 = 0; + if (isImm) + simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); + else + rs2 = fieldFromInstruction(insn, 0, 5); + + // Decode RD. + DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); + if (status != MCDisassembler::Success) + return status; + + // Decode RS1. + status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); + if (status != MCDisassembler::Success) + return status; + + // Decode RS1 | SIMM13. + if (isImm) + MI.addOperand(MCOperand::CreateImm(simm13)); + else { + status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); + if (status != MCDisassembler::Success) + return status; + } + return MCDisassembler::Success; +} diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index fe3227e26b..960261ce98 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -1107,7 +1107,7 @@ let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in def MEMBARi : F3_2<2, 0b101000, (outs), (ins simm13Op:$simm13), "membar $simm13", []>; -let Constraints = "$val = $dst" in { +let Constraints = "$val = $dst", DecoderMethod = "DecodeSWAP" in { def SWAPrr : F3_1<3, 0b001111, (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val), "swap [$addr], $dst", |