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author | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2014-03-01 08:30:58 +0000 |
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committer | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2014-03-01 08:30:58 +0000 |
commit | 830156c66059d4749009dad95ec98e017d306e9b (patch) | |
tree | d4e5e7e313e7959d4e680fe039d1d8d4e35fd8f2 /lib/Target/Sparc | |
parent | abad3545bdf7d89ea9b8c8e0ba30edc45c0118bb (diff) | |
download | llvm-830156c66059d4749009dad95ec98e017d306e9b.tar.gz llvm-830156c66059d4749009dad95ec98e017d306e9b.tar.bz2 llvm-830156c66059d4749009dad95ec98e017d306e9b.tar.xz |
[Sparc] Add support for decoding call instructions in the sparc disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202577 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Sparc')
-rw-r--r-- | lib/Target/Sparc/Disassembler/SparcDisassembler.cpp | 21 | ||||
-rw-r--r-- | lib/Target/Sparc/SparcInstrInfo.td | 5 |
2 files changed, 24 insertions, 2 deletions
diff --git a/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp b/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp index ae07e0b4f7..3c03994e0a 100644 --- a/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp +++ b/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp @@ -190,6 +190,8 @@ static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn, + uint64_t Address, const void *Decoder); #include "SparcGenDisassemblerTables.inc" @@ -336,3 +338,22 @@ static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn, return DecodeMem(Inst, insn, Address, Decoder, false, DecodeQFPRegsRegisterClass); } + +static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, + uint64_t Address, uint64_t Offset, + uint64_t Width, MCInst &MI, + const void *Decoder) { + const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); + return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch, + Offset, Width); +} + +static DecodeStatus DecodeCall(MCInst &MI, unsigned insn, + uint64_t Address, const void *Decoder) { + unsigned tgt = fieldFromInstruction(insn, 0, 30); + tgt <<= 2; + if (!tryAddingSymbolicOperand(tgt+Address, false, Address, + 0, 30, MI, Decoder)) + MI.addOperand(MCOperand::CreateImm(tgt)); + return MCDisassembler::Success; +} diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index 57b692562e..5744fcea18 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -106,6 +106,7 @@ def brtarget : Operand<OtherVT> { def calltarget : Operand<i32> { let EncoderMethod = "getCallTargetOpValue"; + let DecoderMethod = "DecodeCall"; } // Operand for printing out a condition code. @@ -577,8 +578,8 @@ let Uses = [FCC] in // This is the only Format 1 instruction let Uses = [O6], hasDelaySlot = 1, isCall = 1 in { - def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops), - "call $dst", []> { + def CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops), + "call $disp", []> { bits<30> disp; let op = 1; let Inst{29-0} = disp; |