[Sparc] Add support for parsing branches and conditional move instructions with %fcc1-%fcc3 conditional registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202616 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 89 insertions, 44 deletions

diff --git a/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
index 9cbece93a3..901560c5c9 100644
--- a/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
+++ b/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
@@ -68,8 +68,7 @@ class SparcAsmParser : public MCTargetAsmParser {
                StringRef Name);
 
   OperandMatchResultTy
-  parseSparcAsmOperand(SparcOperand *&Operand, bool isCall = false,
-                       bool createTokenForFCC = true);
+  parseSparcAsmOperand(SparcOperand *&Operand, bool isCall = false);
 
   OperandMatchResultTy
   parseBranchModifiers(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
@@ -633,9 +632,7 @@ parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
 
   SparcOperand *Op = 0;
 
-  bool createTokenForFCC = !(Mnemonic == "fcmps" || Mnemonic == "fcmpd"
-                             || Mnemonic == "fcmpq");
-  ResTy = parseSparcAsmOperand(Op, (Mnemonic == "call"), createTokenForFCC);
+  ResTy = parseSparcAsmOperand(Op, (Mnemonic == "call"));
   if (ResTy != MatchOperand_Success || !Op)
     return MatchOperand_ParseFail;
 
@@ -646,8 +643,7 @@ parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
 }
 
 SparcAsmParser::OperandMatchResultTy
-SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op, bool isCall,
-                                     bool createTokenForFCC)
+SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op, bool isCall)
 {
 
   SMLoc S = Parser.getTok().getLoc();
@@ -680,13 +676,6 @@ SparcAsmParser::parseSparcAsmOperand(SparcOperand *&Op, bool isCall,
         else
           Op = SparcOperand::CreateToken("%icc", S);
         break;
-
-      case Sparc::FCC0:
-        if (createTokenForFCC) {
-          assert(name == "fcc0" && "Cannot handle %fcc other than %fcc0 yet");
-          Op = SparcOperand::CreateToken("%fcc0", S);
-          break;
-        }
       }
       break;
     }
diff --git a/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp b/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp
index 66b4b519f7..7a8a66341c 100644
--- a/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp
+++ b/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp
@@ -146,11 +146,12 @@ void SparcInstPrinter::printCCOperand(const MCInst *MI, int opNum,
   case SP::BPFCCA:
   case SP::BPFCCNT:
   case SP::BPFCCANT:
-  case SP::MOVFCCrr:
-  case SP::MOVFCCri:
-  case SP::FMOVS_FCC:
-  case SP::FMOVD_FCC:
-  case SP::FMOVQ_FCC:  // Make sure CC is a fp conditional flag.
+  case SP::MOVFCCrr:  case SP::V9MOVFCCrr:
+  case SP::MOVFCCri:  case SP::V9MOVFCCri:
+  case SP::FMOVS_FCC: case SP::V9FMOVS_FCC:
+  case SP::FMOVD_FCC: case SP::V9FMOVD_FCC:
+  case SP::FMOVQ_FCC: case SP::V9FMOVQ_FCC:
+    // Make sure CC is a fp conditional flag.
     CC = (CC < 16) ? (CC + 16) : CC;
     break;
   }
diff --git a/lib/Target/Sparc/SparcInstrAliases.td b/lib/Target/Sparc/SparcInstrAliases.td
index 93a6c24a08..dc35544daa 100644
--- a/lib/Target/Sparc/SparcInstrAliases.td
+++ b/lib/Target/Sparc/SparcInstrAliases.td
@@ -13,31 +13,52 @@
 // Instruction aliases for conditional moves.
 
 // mov<cond> <ccreg> rs2, rd
-multiclass cond_mov_alias<string cond, int condVal, string ccreg,
+multiclass intcond_mov_alias<string cond, int condVal, string ccreg,
                           Instruction movrr, Instruction movri,
                           Instruction fmovs, Instruction fmovd> {
 
-  // mov<cond> (%icc|%xcc|%fcc0), rs2, rd
+  // mov<cond> (%icc|%xcc), rs2, rd
   def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
                              ", $rs2, $rd"),
                   (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
 
-  // mov<cond> (%icc|%xcc|%fcc0), simm11, rd
+  // mov<cond> (%icc|%xcc), simm11, rd
   def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
                              ", $simm11, $rd"),
                   (movri IntRegs:$rd, i32imm:$simm11, condVal)>;
 
-  // fmovs<cond> (%icc|%xcc|%fcc0), $rs2, $rd
+  // fmovs<cond> (%icc|%xcc), $rs2, $rd
   def : InstAlias<!strconcat(!strconcat(!strconcat("fmovs", cond), ccreg),
                              ", $rs2, $rd"),
                   (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
 
-  // fmovd<cond> (%icc|%xcc|%fcc0), $rs2, $rd
+  // fmovd<cond> (%icc|%xcc), $rs2, $rd
   def : InstAlias<!strconcat(!strconcat(!strconcat("fmovd", cond), ccreg),
                              ", $rs2, $rd"),
                   (fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>;
 }
 
+// mov<cond> <ccreg> rs2, rd
+multiclass fpcond_mov_alias<string cond, int condVal,
+                           Instruction movrr, Instruction movri,
+                           Instruction fmovs, Instruction fmovd> {
+
+  // mov<cond> %fcc[0-3], rs2, rd
+  def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $rs2, $rd"),
+                  (movrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, condVal)>;
+
+  // mov<cond> %fcc[0-3], simm11, rd
+  def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $simm11, $rd"),
+                  (movri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, condVal)>;
+
+  // fmovs<cond> %fcc[0-3], $rs2, $rd
+  def : InstAlias<!strconcat(!strconcat("fmovs", cond), " $cc, $rs2, $rd"),
+                  (fmovs FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, condVal)>;
+
+  // fmovd<cond> %fcc[0-3], $rs2, $rd
+  def : InstAlias<!strconcat(!strconcat("fmovd", cond), " $cc, $rs2, $rd"),
+                  (fmovd DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, condVal)>;
+}
 
 // Instruction aliases for integer conditional branches and moves.
 multiclass int_cond_alias<string cond, int condVal> {
@@ -99,11 +120,11 @@ multiclass int_cond_alias<string cond, int condVal> {
                   (BPXCCANT brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
 
 
-  defm : cond_mov_alias<cond, condVal, " %icc",
+  defm : intcond_mov_alias<cond, condVal, " %icc",
                             MOVICCrr, MOVICCri,
                             FMOVS_ICC, FMOVD_ICC>, Requires<[HasV9]>;
 
-  defm : cond_mov_alias<cond, condVal, " %xcc",
+  defm : intcond_mov_alias<cond, condVal, " %xcc",
                             MOVXCCrr, MOVXCCri,
                             FMOVS_XCC, FMOVD_XCC>, Requires<[Is64Bit]>;
 
@@ -130,36 +151,42 @@ multiclass fp_cond_alias<string cond, int condVal> {
                   (FBCONDA brtarget:$imm, condVal), 0>;
 
   // fb<cond> %fcc0, $imm
-  def : InstAlias<!strconcat(!strconcat("fb", cond), " %fcc0, $imm"),
-                  (BPFCC brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
+  def : InstAlias<!strconcat(!strconcat("fb", cond), " $cc, $imm"),
+                  (BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,
+                  Requires<[HasV9]>;
 
   // fb<cond>,pt %fcc0, $imm
-  def : InstAlias<!strconcat(!strconcat("fb", cond), ",pt %fcc0, $imm"),
-                  (BPFCC brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
+  def : InstAlias<!strconcat(!strconcat("fb", cond), ",pt $cc, $imm"),
+                  (BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,
+                  Requires<[HasV9]>;
 
   // fb<cond>,a %fcc0, $imm
-  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a %fcc0, $imm"),
-                  (BPFCCA brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
+  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $cc, $imm"),
+                  (BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,
+                  Requires<[HasV9]>;
 
   // fb<cond>,a,pt %fcc0, $imm
-  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pt %fcc0, $imm"),
-                  (BPFCCA brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
+  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pt $cc, $imm"),
+                  (BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,
+                   Requires<[HasV9]>;
 
   // fb<cond>,pn %fcc0, $imm
-  def : InstAlias<!strconcat(!strconcat("fb", cond), ",pn %fcc0, $imm"),
-                  (BPFCCNT brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
+  def : InstAlias<!strconcat(!strconcat("fb", cond), ",pn $cc, $imm"),
+                  (BPFCCNT brtarget:$imm, condVal, FCCRegs:$cc)>,
+                   Requires<[HasV9]>;
 
   // fb<cond>,a,pn %fcc0, $imm
-  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pn %fcc0, $imm"),
-                  (BPFCCANT brtarget:$imm, condVal, FCC0)>, Requires<[HasV9]>;
+  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pn $cc, $imm"),
+                  (BPFCCANT brtarget:$imm, condVal, FCCRegs:$cc)>, Requires<[HasV9]>;
 
-  defm : cond_mov_alias<cond, condVal, " %fcc0",
-                        MOVFCCrr, MOVFCCri,
-                        FMOVS_FCC, FMOVD_FCC>, Requires<[HasV9]>;
+  defm : fpcond_mov_alias<cond, condVal,
+                          V9MOVFCCrr, V9MOVFCCri,
+                          V9FMOVS_FCC, V9FMOVD_FCC>, Requires<[HasV9]>;
 
   // fmovq<cond> %fcc0, $rs2, $rd
-  def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %fcc0, $rs2, $rd"),
-                  (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
+  def : InstAlias<!strconcat(!strconcat("fmovq", cond), " $cc, $rs2, $rd"),
+                  (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2,
+                                                          condVal)>,
                   Requires<[HasV9, HasHardQuad]>;
 }
 
diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td
index a27e6abf2b..b4d8ba55fd 100644
--- a/lib/Target/Sparc/SparcInstrInfo.td
+++ b/lib/Target/Sparc/SparcInstrInfo.td
@@ -1019,7 +1019,7 @@ let Predicates = [HasV9] in {
                    Requires<[HasHardQuad]>;
 }
 
-// Floating-point compare instruction with %fcc0-%fcc1
+// Floating-point compare instruction with %fcc0-%fcc3.
 def V9FCMPS  : F3_3c<2, 0b110101, 0b001010001,
                (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
                "fcmps $rd, $rs1, $rs2", []>;
@@ -1031,6 +1031,34 @@ def V9FCMPQ  : F3_3c<2, 0b110101, 0b001010011,
                 "fcmpq $rd, $rs1, $rs2", []>,
                  Requires<[HasHardQuad]>;
 
+// Floating point conditional move instrucitons with %fcc0-%fcc3.
+let Predicates = [HasV9] in {
+  let Constraints = "$f = $rd", intcc = 0 in {
+    def V9MOVFCCrr
+      : F4_1<0b101100, (outs IntRegs:$rd),
+             (ins FCCRegs:$cc, IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
+             "mov$cond $cc, $rs2, $rd", []>;
+    def V9MOVFCCri
+      : F4_2<0b101100, (outs IntRegs:$rd),
+             (ins FCCRegs:$cc, i32imm:$simm11, IntRegs:$f, CCOp:$cond),
+             "mov$cond $cc, $simm11, $rd", []>;
+    def V9FMOVS_FCC
+      : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
+             (ins FCCRegs:$opf_cc, FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
+             "fmovs$cond $opf_cc, $rs2, $rd", []>;
+    def V9FMOVD_FCC
+      : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
+             (ins FCCRegs:$opf_cc, DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
+             "fmovd$cond $opf_cc, $rs2, $rd", []>;
+    def V9FMOVQ_FCC
+      : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
+             (ins FCCRegs:$opf_cc, QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
+             "fmovq$cond $opf_cc, $rs2, $rd", []>,
+             Requires<[HasHardQuad]>;
+  } // Constraints = "$f = $rd", ...
+} // let Predicates = [hasV9]
+
+
 // POPCrr - This does a ctpop of a 64-bit register.  As such, we have to clear
 // the top 32-bits before using it.  To do this clearing, we use a SRLri X,0.
 let rs1 = 0 in