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| author | Evan Cheng <evan.cheng@apple.com> | 2011-06-24 01:44:41 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2011-06-24 01:44:41 +0000 |
| commit | a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576d (patch) | |
| tree | 843b1f6be5ffffef461ce063cf5468368598d40e /lib/Target/Sparc | |
| parent | 66dddd1da3e036d05f94df82221a97b7d26e3498 (diff) | |
| download | llvm-a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576d.tar.gz llvm-a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576d.tar.bz2 llvm-a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576d.tar.xz | |
Starting to refactor Target to separate out code that's needed to fully describe
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.
First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Sparc')
| -rw-r--r-- | lib/Target/Sparc/CMakeLists.txt | 5 | ||||
| -rw-r--r-- | lib/Target/Sparc/Makefile | 3 | ||||
| -rw-r--r-- | lib/Target/Sparc/SparcRegisterInfo.cpp | 8 |
3 files changed, 9 insertions, 7 deletions
diff --git a/lib/Target/Sparc/CMakeLists.txt b/lib/Target/Sparc/CMakeLists.txt index 6839234a47..243e889723 100644 --- a/lib/Target/Sparc/CMakeLists.txt +++ b/lib/Target/Sparc/CMakeLists.txt @@ -1,8 +1,9 @@ set(LLVM_TARGET_DEFINITIONS Sparc.td) -tablegen(SparcGenRegisterInfo.h.inc -gen-register-desc-header) tablegen(SparcGenRegisterNames.inc -gen-register-enums) -tablegen(SparcGenRegisterInfo.inc -gen-register-desc) +tablegen(SparcGenRegisterDesc.inc -gen-register-desc) +tablegen(SparcGenRegisterInfo.h.inc -gen-register-info-header) +tablegen(SparcGenRegisterInfo.inc -gen-register-info) tablegen(SparcGenInstrNames.inc -gen-instr-enums) tablegen(SparcGenInstrInfo.inc -gen-instr-desc) tablegen(SparcGenAsmWriter.inc -gen-asm-writer) diff --git a/lib/Target/Sparc/Makefile b/lib/Target/Sparc/Makefile index 27942c56fb..af7d9daa3d 100644 --- a/lib/Target/Sparc/Makefile +++ b/lib/Target/Sparc/Makefile @@ -13,7 +13,8 @@ TARGET = Sparc # Make sure that tblgen is run, first thing. BUILT_SOURCES = SparcGenRegisterInfo.h.inc SparcGenRegisterNames.inc \ - SparcGenRegisterInfo.inc SparcGenInstrNames.inc \ + SparcGenRegisterInfo.inc SparcGenRegisterDesc.inc \ + SparcGenInstrNames.inc \ SparcGenInstrInfo.inc SparcGenAsmWriter.inc \ SparcGenDAGISel.inc SparcGenSubtarget.inc SparcGenCallingConv.inc diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp index 9fcf028fa6..c63f52e958 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -23,11 +23,14 @@ #include "llvm/Type.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" +#include "SparcGenRegisterDesc.inc" +#include "SparcGenRegisterInfo.inc" using namespace llvm; SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st, const TargetInstrInfo &tii) - : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), + : SparcGenRegisterInfo(SparcRegDesc, SparcRegInfoDesc, + SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), Subtarget(st), TII(tii) { } @@ -135,6 +138,3 @@ int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { int SparcRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { return SparcGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0); } - -#include "SparcGenRegisterInfo.inc" - |