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author | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2013-08-20 01:26:14 +0000 |
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committer | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2013-08-20 01:26:14 +0000 |
commit | e3b29fbc5f4d7632a88b6f470a96cc6ac09e31ed (patch) | |
tree | 5835b66e9d54a50e062da9f2e1c1c659e244e87d /lib/Target/Sparc | |
parent | ec28c7d8ecaa75e7648c063130a285305743469b (diff) | |
download | llvm-e3b29fbc5f4d7632a88b6f470a96cc6ac09e31ed.tar.gz llvm-e3b29fbc5f4d7632a88b6f470a96cc6ac09e31ed.tar.bz2 llvm-e3b29fbc5f4d7632a88b6f470a96cc6ac09e31ed.tar.xz |
[Sparc] Use HWEncoding instead of unused Num field in Sparc register definitions. Also, correct the definitions of RETL and RET instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188738 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Sparc')
-rw-r--r-- | lib/Target/Sparc/SparcInstrInfo.td | 4 | ||||
-rw-r--r-- | lib/Target/Sparc/SparcRegisterInfo.td | 17 |
2 files changed, 9 insertions, 12 deletions
diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index d4cac4d3ba..2d228eabb9 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -286,11 +286,11 @@ let usesCustomInserter = 1, Uses = [FCC] in { // Section A.3 - Synthetic Instructions, p. 85 // special cases of JMPL: let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in { - let rd = O7.Num, rs1 = G0.Num in + let rd = 0, rs1 = 15 in def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val), "jmp %o7+$val", [(retflag simm13:$val)]>; - let rd = I7.Num, rs1 = G0.Num in + let rd = 0, rs1 = 31 in def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val), "jmp %i7+$val", []>; } diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td index a59c4426f0..b239f80db5 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.td +++ b/lib/Target/Sparc/SparcRegisterInfo.td @@ -11,8 +11,8 @@ // Declarations that describe the Sparc register file //===----------------------------------------------------------------------===// -class SparcReg<string n> : Register<n> { - field bits<5> Num; +class SparcReg<bits<16> Enc, string n> : Register<n> { + let HWEncoding = Enc; let Namespace = "SP"; } @@ -27,16 +27,13 @@ def sub_odd : SubRegIndex<32, 32>; // Registers are identified with 5-bit ID numbers. // Ri - 32-bit integer registers -class Ri<bits<5> num, string n> : SparcReg<n> { - let Num = num; -} +class Ri<bits<16> Enc, string n> : SparcReg<Enc, n>; + // Rf - 32-bit floating-point registers -class Rf<bits<5> num, string n> : SparcReg<n> { - let Num = num; -} +class Rf<bits<16> Enc, string n> : SparcReg<Enc, n>; + // Rd - Slots in the FP register file for 64-bit floating-point values. -class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> { - let Num = num; +class Rd<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> { let SubRegs = subregs; let SubRegIndices = [sub_even, sub_odd]; let CoveredBySubRegs = 1; |