[SystemZ] Postpone NI->RISBG conversion to convertToThreeAddress()

r186399 aggressively used the RISBG instruction for immediate ANDs,
both because it can handle some values that AND IMMEDIATE can't,
and because it allows the destination register to be different from
the source.  I realized later while implementing the distinct-ops
support that it would be better to leave the choice up to
convertToThreeAddress() instead.  The AND IMMEDIATE form is shorter
and is less likely to be cracked.

This is a problem for 32-bit ANDs because we assume that all 32-bit
operations will leave the high word untouched, whereas RISBG used in
this way will either clear the high word or copy it from the source
register.  The patch uses the z196 instruction RISBLG for this instead.

This means that z10 will be restricted to NILL, NILH and NILF for
32-bit ANDs, but I think that should be OK for now.  Although we're
using z10 as the base architecture, the optimization work is going
to be focused more on z196 and zEC12.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187492 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 127 insertions, 13 deletions

diff --git a/lib/Target/SystemZ/SystemZInstrInfo.cpp b/lib/Target/SystemZ/SystemZInstrInfo.cpp
index 26ea086aa3..12211fe2c2 100644
--- a/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -23,6 +23,11 @@
 
 using namespace llvm;
 
+// Return a mask with Count low bits set.
+static uint64_t allOnes(unsigned int Count) {
+  return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
+}
+
 SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
   : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
     RI(tm), TM(tm) {
@@ -507,6 +512,49 @@ static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
           MI->getOperand(3).getReg() == 0);
 }
 
+namespace {
+  struct LogicOp {
+    LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {}
+    LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
+      : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
+
+    operator bool() const { return RegSize; }
+
+    unsigned RegSize, ImmLSB, ImmSize;
+  };
+}
+
+static LogicOp interpretAndImmediate(unsigned Opcode) {
+  switch (Opcode) {
+  case SystemZ::NILL32: return LogicOp(32,  0, 16);
+  case SystemZ::NILH32: return LogicOp(32, 16, 16);
+  case SystemZ::NILL:   return LogicOp(64,  0, 16);
+  case SystemZ::NILH:   return LogicOp(64, 16, 16);
+  case SystemZ::NIHL:   return LogicOp(64, 32, 16);
+  case SystemZ::NIHH:   return LogicOp(64, 48, 16);
+  case SystemZ::NILF32: return LogicOp(32,  0, 32);
+  case SystemZ::NILF:   return LogicOp(64,  0, 32);
+  case SystemZ::NIHF:   return LogicOp(64, 32, 32);
+  default:              return LogicOp();
+  }
+}
+
+// Used to return from convertToThreeAddress after replacing two-address
+// instruction OldMI with three-address instruction NewMI.
+static MachineInstr *finishConvertToThreeAddress(MachineInstr *OldMI,
+                                                 MachineInstr *NewMI,
+                                                 LiveVariables *LV) {
+  if (LV) {
+    unsigned NumOps = OldMI->getNumOperands();
+    for (unsigned I = 1; I < NumOps; ++I) {
+      MachineOperand &Op = OldMI->getOperand(I);
+      if (Op.isReg() && Op.isKill())
+        LV->replaceKillInstruction(Op.getReg(), OldMI, NewMI);
+    }
+  }
+  return NewMI;
+}
+
 MachineInstr *
 SystemZInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
                                         MachineBasicBlock::iterator &MBBI,
@@ -524,26 +572,50 @@ SystemZInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
   if (TM.getSubtargetImpl()->hasDistinctOps()) {
     int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
     if (ThreeOperandOpcode >= 0) {
-      unsigned DestReg = MI->getOperand(0).getReg();
+      MachineOperand &Dest = MI->getOperand(0);
       MachineOperand &Src = MI->getOperand(1);
-      MachineInstrBuilder MIB = BuildMI(*MBB, MBBI, MI->getDebugLoc(),
-                                        get(ThreeOperandOpcode), DestReg);
+      MachineInstrBuilder MIB =
+        BuildMI(*MBB, MBBI, MI->getDebugLoc(), get(ThreeOperandOpcode))
+        .addOperand(Dest);
       // Keep the kill state, but drop the tied flag.
-      MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()));
+      MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg());
       // Keep the remaining operands as-is.
       for (unsigned I = 2; I < NumOps; ++I)
         MIB.addOperand(MI->getOperand(I));
-      MachineInstr *NewMI = MIB;
-
-      // Transfer killing information to the new instruction.
-      if (LV) {
-        for (unsigned I = 1; I < NumOps; ++I) {
-          MachineOperand &Op = MI->getOperand(I);
-          if (Op.isReg() && Op.isKill())
-            LV->replaceKillInstruction(Op.getReg(), MI, NewMI);
+      return finishConvertToThreeAddress(MI, MIB, LV);
+    }
+  }
+
+  // Try to convert an AND into an RISBG-type instruction.
+  if (LogicOp And = interpretAndImmediate(Opcode)) {
+    unsigned NewOpcode;
+    if (And.RegSize == 64)
+      NewOpcode = SystemZ::RISBG;
+    else if (TM.getSubtargetImpl()->hasHighWord())
+      NewOpcode = SystemZ::RISBLG32;
+    else
+      // We can't use RISBG for 32-bit operations because it clobbers the
+      // high word of the destination too.
+      NewOpcode = 0;
+    if (NewOpcode) {
+      uint64_t Imm = MI->getOperand(2).getImm() << And.ImmLSB;
+      // AND IMMEDIATE leaves the other bits of the register unchanged.
+      Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
+      unsigned Start, End;
+      if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
+        if (NewOpcode == SystemZ::RISBLG32) {
+          Start &= 31;
+          End &= 31;
         }
+        MachineOperand &Dest = MI->getOperand(0);
+        MachineOperand &Src = MI->getOperand(1);
+        MachineInstrBuilder MIB =
+          BuildMI(*MBB, MI, MI->getDebugLoc(), get(NewOpcode))
+          .addOperand(Dest).addReg(0)
+          .addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg())
+          .addImm(Start).addImm(End + 128).addImm(0);
+        return finishConvertToThreeAddress(MI, MIB, LV);
       }
-      return MIB;
     }
   }
   return 0;
@@ -775,6 +847,48 @@ unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
   return 0;
 }
 
+// Return true if Mask matches the regexp 0*1+0*, given that zero masks
+// have already been filtered out.  Store the first set bit in LSB and
+// the number of set bits in Length if so.
+static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
+  unsigned First = findFirstSet(Mask);
+  uint64_t Top = (Mask >> First) + 1;
+  if ((Top & -Top) == Top) {
+    LSB = First;
+    Length = findFirstSet(Top);
+    return true;
+  }
+  return false;
+}
+
+bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize,
+                                   unsigned &Start, unsigned &End) const {
+  // Reject trivial all-zero masks.
+  if (Mask == 0)
+    return false;
+
+  // Handle the 1+0+ or 0+1+0* cases.  Start then specifies the index of
+  // the msb and End specifies the index of the lsb.
+  unsigned LSB, Length;
+  if (isStringOfOnes(Mask, LSB, Length)) {
+    Start = 63 - (LSB + Length - 1);
+    End = 63 - LSB;
+    return true;
+  }
+
+  // Handle the wrap-around 1+0+1+ cases.  Start then specifies the msb
+  // of the low 1s and End specifies the lsb of the high 1s.
+  if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) {
+    assert(LSB > 0 && "Bottom bit must be set");
+    assert(LSB + Length < BitSize && "Top bit must be set");
+    Start = 63 - (LSB - 1);
+    End = 63 - (LSB + Length);
+    return true;
+  }
+
+  return false;
+}
+
 unsigned SystemZInstrInfo::getCompareAndBranch(unsigned Opcode,
                                                const MachineInstr *MI) const {
   switch (Opcode) {