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authorBill Wendling <isanbard@gmail.com>2013-06-07 20:42:15 +0000
committerBill Wendling <isanbard@gmail.com>2013-06-07 20:42:15 +0000
commitfc61b6f111af79662baf273c40593a1e8f4dc719 (patch)
tree455c0fd93c8addc3c6c6801ccea7ea472fad371b /lib/Target/SystemZ/SystemZInstrInfo.cpp
parent3ff0abfaabc2c7f604d490be587b9c27e7c91ac0 (diff)
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Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183567 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/SystemZ/SystemZInstrInfo.cpp')
-rw-r--r--lib/Target/SystemZ/SystemZInstrInfo.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/SystemZ/SystemZInstrInfo.cpp b/lib/Target/SystemZ/SystemZInstrInfo.cpp
index 5339bf14ac..0d30432354 100644
--- a/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -23,7 +23,7 @@ using namespace llvm;
SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
: SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
- RI(tm, *this) {
+ RI(tm) {
}
// MI is a 128-bit load or store. Split it into two 64-bit loads or stores,