[SystemZ] Define the GR64 low-word logic instructions as pseudo aliases.

Another patch to avoid duplication of encoding information.  Things like
NILF, NILL and NILH are used as both 32-bit and 64-bit instructions.
Here the 64-bit versions are defined as aliases of the 32-bit ones.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191369 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 8 insertions, 0 deletions

diff --git a/lib/Target/SystemZ/SystemZPatterns.td b/lib/Target/SystemZ/SystemZPatterns.td
index a1344a3a8e..203247c502 100644
--- a/lib/Target/SystemZ/SystemZPatterns.td
+++ b/lib/Target/SystemZ/SystemZPatterns.td
@@ -112,6 +112,14 @@ multiclass CondStores64<Instruction insn, Instruction insninv,
                      uimm8zx4:$valid, uimm8zx4:$cc)>;
 }
 
+// INSN performs a comparison between a 32-bit register and a constant.
+// Record that it is equivalent to comparing the low word of a GR64 with IMM.
+class CompareGR64RI<Instruction insn, SDPatternOperator compare,
+                    Immediate imm>
+  : Pat<(compare GR64:$R1, imm:$I2),
+        (insn (EXTRACT_SUBREG GR64:$R1, subreg_32bit),
+              (imm.OperandTransform imm:$I2))>;
+
 // Try to use MVC instruction INSN for a load of type LOAD followed by a store
 // of the same size.  VT is the type of the intermediate (legalized) value and
 // LENGTH is the number of bytes loaded by LOAD.