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authorRichard Sandiford <rsandifo@linux.vnet.ibm.com>2013-09-06 11:51:39 +0000
committerRichard Sandiford <rsandifo@linux.vnet.ibm.com>2013-09-06 11:51:39 +0000
commitaff1c6427ce22125adfa29de4145030aa3214a2e (patch)
treefa79c736f4b56993d88ddb763d8efb044850d255 /lib/Target/SystemZ/SystemZPatterns.td
parente3273b327555df6489640d2195b52b6317c88844 (diff)
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[SystemZ] Tweak integer comparison code
The architecture has many comparison instructions, including some that extend one of the operands. The signed comparison instructions use sign extensions and the unsigned comparison instructions use zero extensions. In cases where we had a free choice between signed or unsigned comparisons, we were trying to decide at lowering time which would best fit the available instructions, taking things like extension type into account. The code to do that was getting increasingly hairy and was also making some bad decisions. E.g. when comparing the result of two LLCs, it is better to use CR rather than CLR, since CR can be fused with a branch while CLR can't. This patch removes the lowering code and instead adds an operand to integer comparisons to say whether signed comparison is required, whether unsigned comparison is required, or whether either is OK. We can then leave the choice of instruction up to the normal isel code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190138 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/SystemZ/SystemZPatterns.td')
-rw-r--r--lib/Target/SystemZ/SystemZPatterns.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/SystemZ/SystemZPatterns.td b/lib/Target/SystemZ/SystemZPatterns.td
index bc3775f279..481534b26a 100644
--- a/lib/Target/SystemZ/SystemZPatterns.td
+++ b/lib/Target/SystemZ/SystemZPatterns.td
@@ -103,4 +103,4 @@ multiclass BlockLoadStore<SDPatternOperator load, ValueType vt,
// registers in CLS against zero. The instruction has separate R1 and R2
// operands, but they must be the same when the instruction is used like this.
class CompareZeroFP<Instruction insn, RegisterOperand cls>
- : Pat<(z_cmp cls:$reg, (fpimm0)), (insn cls:$reg, cls:$reg)>;
+ : Pat<(z_fcmp cls:$reg, (fpimm0)), (insn cls:$reg, cls:$reg)>;