[SystemZ] Add LOC and LOCG

As with the stores, these instructions can trap when the condition is false,
so they are only used for things like (cond ? x : *ptr).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187112 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 12 insertions, 0 deletions

diff --git a/lib/Target/SystemZ/SystemZPatterns.td b/lib/Target/SystemZ/SystemZPatterns.td
index 74cc5f019a..4e4386a398 100644
--- a/lib/Target/SystemZ/SystemZPatterns.td
+++ b/lib/Target/SystemZ/SystemZPatterns.td
@@ -54,6 +54,18 @@ multiclass RMWIByte<SDPatternOperator operator, AddressingMode mode,
   def : RMWI<anyextloadi8, operator, truncstorei8, mode, imm64, insn>;
 }
 
+// Record that INSN conditionally performs load operation LOAD into a
+// register of class CLS.  The load may trap even if the condition is false.
+multiclass CondLoad<Instruction insn, RegisterOperand cls,
+                    SDPatternOperator load> {
+  def : Pat<(z_select_ccmask (load bdaddr20only:$addr), cls:$new, uimm8zx4:$cc),
+            (insn cls:$new, bdaddr20only:$addr, uimm8zx4:$cc)>,
+        Requires<[FeatureLoadStoreOnCond]>;
+  def : Pat<(z_select_ccmask cls:$new, (load bdaddr20only:$addr), uimm8zx4:$cc),
+            (insn cls:$new, bdaddr20only:$addr, (INVCC uimm8zx4:$cc))>,
+        Requires<[FeatureLoadStoreOnCond]>;
+}
+
 // Record that INSN performs insertion TYPE into a register of class CLS.
 // The inserted operand is loaded using LOAD from an address of mode MODE.
 multiclass InsertMem<string type, Instruction insn, RegisterOperand cls,