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author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-09-30 08:48:38 +0000 |
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committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-09-30 08:48:38 +0000 |
commit | 514756983e9ba3684a89ed583bf5a98ffb20c203 (patch) | |
tree | 924fc41da9747d8fbdccae0316eabbc2dc67629b /lib/Target/SystemZ/SystemZRegisterInfo.cpp | |
parent | 39004b537beb1acc26675c8943c2cce4ca8a0499 (diff) | |
download | llvm-514756983e9ba3684a89ed583bf5a98ffb20c203.tar.gz llvm-514756983e9ba3684a89ed583bf5a98ffb20c203.tar.bz2 llvm-514756983e9ba3684a89ed583bf5a98ffb20c203.tar.xz |
[SystemZ] Rename 32-bit GPR registers
I'm about to add support for high-word operations, so it seemed better
for the low-word registers to have names like R0L rather than R0W.
No behavioral change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191655 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/SystemZ/SystemZRegisterInfo.cpp')
-rw-r--r-- | lib/Target/SystemZ/SystemZRegisterInfo.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.cpp b/lib/Target/SystemZ/SystemZRegisterInfo.cpp index 8ce6d6ab44..841f0ae026 100644 --- a/lib/Target/SystemZ/SystemZRegisterInfo.cpp +++ b/lib/Target/SystemZ/SystemZRegisterInfo.cpp @@ -42,13 +42,13 @@ SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const { if (TFI->hasFP(MF)) { // R11D is the frame pointer. Reserve all aliases. Reserved.set(SystemZ::R11D); - Reserved.set(SystemZ::R11W); + Reserved.set(SystemZ::R11L); Reserved.set(SystemZ::R10Q); } // R15D is the stack pointer. Reserve all aliases. Reserved.set(SystemZ::R15D); - Reserved.set(SystemZ::R15W); + Reserved.set(SystemZ::R15L); Reserved.set(SystemZ::R14Q); return Reserved; } |