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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-15 18:02:56 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-15 18:02:56 +0000 |
commit | b79e30cc9e8ce8c6beacbc38a7e27d33ba07fd66 (patch) | |
tree | 66b3cda296885b021265a5fa4a490d1439cc7941 /lib/Target/SystemZ/SystemZRegisterInfo.cpp | |
parent | f60ceac9cd7230e0d5ff911fced396f6b5d8c815 (diff) | |
download | llvm-b79e30cc9e8ce8c6beacbc38a7e27d33ba07fd66.tar.gz llvm-b79e30cc9e8ce8c6beacbc38a7e27d33ba07fd66.tar.bz2 llvm-b79e30cc9e8ce8c6beacbc38a7e27d33ba07fd66.tar.xz |
Remove custom allocation orders in SystemZ.
Note that this actually changes code generation, and someone who
understands this target better should check the changes.
- R12Q is now allocatable. I think it was omitted from the allocation
order by mistake since it isn't reserved. It as apparently used as a
GOT pointer sometimes, and it should probably be reserved if that is
the case.
- The GR64 registers are allocated in a different order now. The
register allocator will automatically put the CSRs last. There were
other changes to the order that may have been significant.
The test fix is because r0 and r1 swapped places in the allocation order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133067 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/SystemZ/SystemZRegisterInfo.cpp')
-rw-r--r-- | lib/Target/SystemZ/SystemZRegisterInfo.cpp | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.cpp b/lib/Target/SystemZ/SystemZRegisterInfo.cpp index ed62cfff08..d5c165f640 100644 --- a/lib/Target/SystemZ/SystemZRegisterInfo.cpp +++ b/lib/Target/SystemZ/SystemZRegisterInfo.cpp @@ -51,10 +51,20 @@ BitVector SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const BitVector Reserved(getNumRegs()); const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); - if (TFI->hasFP(MF)) + if (TFI->hasFP(MF)) { + // R11D is the frame pointer. Reserve all aliases. Reserved.set(SystemZ::R11D); + Reserved.set(SystemZ::R11W); + Reserved.set(SystemZ::R10P); + Reserved.set(SystemZ::R10Q); + } + Reserved.set(SystemZ::R14D); Reserved.set(SystemZ::R15D); + Reserved.set(SystemZ::R14W); + Reserved.set(SystemZ::R15W); + Reserved.set(SystemZ::R14P); + Reserved.set(SystemZ::R14Q); return Reserved; } |