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authorDavid Woodhouse <dwmw2@infradead.org>2014-01-08 12:58:24 +0000
committerDavid Woodhouse <dwmw2@infradead.org>2014-01-08 12:58:24 +0000
commitaab59870a4f57f3d3246c858cb775766e38f0795 (patch)
treeefd5c5c5a8c4abba9970b576950e1072fe941865 /lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
parent4f32ce2436d11f4de00db677f2c1d0a4022dbcfe (diff)
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[x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand
It seems there is no separate instruction class for having AdSize *and* OpSize bits set, which is required in order to disambiguate between all these instructions. So add that to the disassembler. Hm, perhaps we do need an AdSize16 bit after all? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198759 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h')
-rw-r--r--lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h b/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
index 1acaef1b94..954a3d7ac5 100644
--- a/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
+++ b/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
@@ -92,6 +92,8 @@ enum attributeBits {
"operands change width") \
ENUM_ENTRY(IC_ADSIZE, 3, "requires an ADSIZE prefix, so " \
"operands change width") \
+ ENUM_ENTRY(IC_OPSIZE_ADSIZE, 3, "requires both OPSIZE and ADSIZE " \
+ "prefixes") \
ENUM_ENTRY(IC_XD, 2, "may say something about the opcode " \
"but not the operands") \
ENUM_ENTRY(IC_XS, 2, "may say something about the opcode " \