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| author | Evan Cheng <evan.cheng@apple.com> | 2011-07-27 23:22:03 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2011-07-27 23:22:03 +0000 |
| commit | 5de728cfe1a922ac9b13546dca94526b2fa693b6 (patch) | |
| tree | b6de43d668add172ad80b6708b82936bcc918b5f /lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | |
| parent | ed398468b51c6eb5b2c9a5bccc8669854cf589a8 (diff) | |
| download | llvm-5de728cfe1a922ac9b13546dca94526b2fa693b6.tar.gz llvm-5de728cfe1a922ac9b13546dca94526b2fa693b6.tar.bz2 llvm-5de728cfe1a922ac9b13546dca94526b2fa693b6.tar.xz | |
Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.
This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.
rdar://8204588
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136292 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp')
| -rw-r--r-- | lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp index bd7ee0a549..cf582b5844 100644 --- a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp +++ b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp @@ -155,11 +155,6 @@ static MCFixupKind getImmFixupKind(uint64_t TSFlags) { return MCFixup::getKindForSize(Size, isPCRel); } -namespace llvm { - // FIXME: TableGen this? - extern MCRegisterClass X86MCRegisterClasses[]; // In X86GenRegisterInfo.inc. -} - /// Is32BitMemOperand - Return true if the specified instruction with a memory /// operand should emit the 0x67 prefix byte in 64-bit mode due to a 32-bit /// memory operand. Op specifies the operand # of the memoperand. |