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| author | Yunzhong Gao <Yunzhong_Gao@playstation.sony.com> | 2013-09-27 18:38:42 +0000 |
|---|---|---|
| committer | Yunzhong Gao <Yunzhong_Gao@playstation.sony.com> | 2013-09-27 18:38:42 +0000 |
| commit | 685707c28e2c7117f025fb4e95e6ca64ed179bb0 (patch) | |
| tree | 1b3bf3d5abf0ab4b443d820430e0245656941640 /lib/Target/X86/MCTargetDesc | |
| parent | 9e81c3bdb216e7ca457acf6614591e5b807cf70c (diff) | |
| download | llvm-685707c28e2c7117f025fb4e95e6ca64ed179bb0.tar.gz llvm-685707c28e2c7117f025fb4e95e6ca64ed179bb0.tar.bz2 llvm-685707c28e2c7117f025fb4e95e6ca64ed179bb0.tar.xz | |
Adding intrinsics to the llvm backend for TBM instruction set.
Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191539 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/MCTargetDesc')
| -rw-r--r-- | lib/Target/X86/MCTargetDesc/X86BaseInfo.h | 3 | ||||
| -rw-r--r-- | lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/lib/Target/X86/MCTargetDesc/X86BaseInfo.h b/lib/Target/X86/MCTargetDesc/X86BaseInfo.h index 25d1af3938..1ef98141f8 100644 --- a/lib/Target/X86/MCTargetDesc/X86BaseInfo.h +++ b/lib/Target/X86/MCTargetDesc/X86BaseInfo.h @@ -354,6 +354,9 @@ namespace X86II { // XOP9 - Prefix to exclude use of imm byte. XOP9 = 21 << Op0Shift, + // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions. + XOPA = 22 << Op0Shift, + //===------------------------------------------------------------------===// // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. // They are used to specify GPRs and SSE registers, 64-bit operand size, diff --git a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp index 0c9fd91e31..032c52cf85 100644 --- a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp +++ b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp @@ -665,6 +665,9 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, case X86II::XOP9: VEX_5M = 0x9; break; + case X86II::XOPA: + VEX_5M = 0xA; + break; case X86II::A6: // Bypass: Not used by VEX case X86II::A7: // Bypass: Not used by VEX case X86II::TB: // Bypass: Not used by VEX |