Modify the two address instruction pass to remove the duplicate

operand of the instruction and thus simplify the register allocation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11124 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 25 insertions, 8 deletions

diff --git a/lib/Target/X86/PeepholeOptimizer.cpp b/lib/Target/X86/PeepholeOptimizer.cpp
index 89008aeeca..6d07ec502a 100644
--- a/lib/Target/X86/PeepholeOptimizer.cpp
+++ b/lib/Target/X86/PeepholeOptimizer.cpp
@@ -67,15 +67,35 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
     // immediate despite the fact that the operands are 16 or 32 bits.  Because
     // this can save three bytes of code size (and icache space), we want to
     // shrink them if possible.
+  case X86::IMULri16: case X86::IMULri32:
+    assert(MI->getNumOperands() == 3 && "These should all have 3 operands!");
+    if (MI->getOperand(2).isImmediate()) {
+      int Val = MI->getOperand(2).getImmedValue();
+      // If the value is the same when signed extended from 8 bits...
+      if (Val == (signed int)(signed char)Val) {
+        unsigned Opcode;
+        switch (MI->getOpcode()) {
+        default: assert(0 && "Unknown opcode value!");
+        case X86::IMULri16: Opcode = X86::IMULri16b; break;
+        case X86::IMULri32: Opcode = X86::IMULri32b; break;
+        }
+        unsigned R0 = MI->getOperand(0).getReg();
+        unsigned R1 = MI->getOperand(1).getReg();
+        *I = BuildMI(Opcode, 2, R0).addReg(R1).addZImm((char)Val);
+        delete MI;
+        return true;
+      }
+    }
+    return false;
+
   case X86::ADDri16:  case X86::ADDri32:
   case X86::SUBri16:  case X86::SUBri32:
-  case X86::IMULri16: case X86::IMULri32:
   case X86::ANDri16:  case X86::ANDri32:
   case X86::ORri16:   case X86::ORri32:
   case X86::XORri16:  case X86::XORri32:
-    assert(MI->getNumOperands() == 3 && "These should all have 3 operands!");
-    if (MI->getOperand(2).isImmediate()) {
-      int Val = MI->getOperand(2).getImmedValue();
+    assert(MI->getNumOperands() == 2 && "These should all have 2 operands!");
+    if (MI->getOperand(1).isImmediate()) {
+      int Val = MI->getOperand(1).getImmedValue();
       // If the value is the same when signed extended from 8 bits...
       if (Val == (signed int)(signed char)Val) {
         unsigned Opcode;
@@ -85,8 +105,6 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
         case X86::ADDri32:  Opcode = X86::ADDri32b; break;
         case X86::SUBri16:  Opcode = X86::SUBri16b; break;
         case X86::SUBri32:  Opcode = X86::SUBri32b; break;
-        case X86::IMULri16: Opcode = X86::IMULri16b; break;
-        case X86::IMULri32: Opcode = X86::IMULri32b; break;
         case X86::ANDri16:  Opcode = X86::ANDri16b; break;
         case X86::ANDri32:  Opcode = X86::ANDri32b; break;
         case X86::ORri16:   Opcode = X86::ORri16b; break;
@@ -95,8 +113,7 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
         case X86::XORri32:  Opcode = X86::XORri32b; break;
         }
         unsigned R0 = MI->getOperand(0).getReg();
-        unsigned R1 = MI->getOperand(1).getReg();
-        *I = BuildMI(Opcode, 2, R0).addReg(R1).addZImm((char)Val);
+        *I = BuildMI(Opcode, 1, R0, MOTy::UseAndDef).addZImm((char)Val);
         delete MI;
         return true;
       }