Rename the IMULri* instructions to IMULrri, as they are actually three address

instructions.  Add forms of these instructions that read from memory


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11518 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 28 insertions, 3 deletions

diff --git a/lib/Target/X86/PeepholeOptimizer.cpp b/lib/Target/X86/PeepholeOptimizer.cpp
index accbdd6dcc..512a721366 100644
--- a/lib/Target/X86/PeepholeOptimizer.cpp
+++ b/lib/Target/X86/PeepholeOptimizer.cpp
@@ -72,7 +72,7 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
     // immediate despite the fact that the operands are 16 or 32 bits.  Because
     // this can save three bytes of code size (and icache space), we want to
     // shrink them if possible.
-  case X86::IMULri16: case X86::IMULri32:
+  case X86::IMULrri16: case X86::IMULrri32:
     assert(MI->getNumOperands() == 3 && "These should all have 3 operands!");
     if (MI->getOperand(2).isImmediate()) {
       int Val = MI->getOperand(2).getImmedValue();
@@ -81,8 +81,8 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
         unsigned Opcode;
         switch (MI->getOpcode()) {
         default: assert(0 && "Unknown opcode value!");
-        case X86::IMULri16: Opcode = X86::IMULri16b; break;
-        case X86::IMULri32: Opcode = X86::IMULri32b; break;
+        case X86::IMULrri16: Opcode = X86::IMULrri16b; break;
+        case X86::IMULrri32: Opcode = X86::IMULrri32b; break;
         }
         unsigned R0 = MI->getOperand(0).getReg();
         unsigned R1 = MI->getOperand(1).getReg();
@@ -93,6 +93,31 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
     }
     return false;
 
+  case X86::IMULrmi16: case X86::IMULrmi32:
+    assert(MI->getNumOperands() == 6 && "These should all have 6 operands!");
+    if (MI->getOperand(5).isImmediate()) {
+      int Val = MI->getOperand(5).getImmedValue();
+      // If the value is the same when signed extended from 8 bits...
+      if (Val == (signed int)(signed char)Val) {
+        unsigned Opcode;
+        switch (MI->getOpcode()) {
+        default: assert(0 && "Unknown opcode value!");
+        case X86::IMULrmi16: Opcode = X86::IMULrmi16b; break;
+        case X86::IMULrmi32: Opcode = X86::IMULrmi32b; break;
+        }
+        unsigned R0 = MI->getOperand(0).getReg();
+        unsigned R1 = MI->getOperand(1).getReg();
+        unsigned Scale = MI->getOperand(2).getImmedValue();
+        unsigned R2 = MI->getOperand(3).getReg();
+        unsigned Offset = MI->getOperand(3).getImmedValue();
+        I = MBB.insert(MBB.erase(I),
+                       BuildMI(Opcode, 2, R0).addReg(R1).addZImm(Scale).
+                             addReg(R2).addSImm(Offset).addZImm((char)Val));
+        return true;
+      }
+    }
+    return false;
+
   case X86::ADDri16:  case X86::ADDri32:
   case X86::ADDmi16:  case X86::ADDmi32:
   case X86::SUBri16:  case X86::SUBri32: