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author | Chris Lattner <sabre@nondot.org> | 2004-02-22 04:44:58 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2004-02-22 04:44:58 +0000 |
commit | 6d2fdcfb8a922570d3a60540d36eb7804e7296f2 (patch) | |
tree | 10e3c74a80de3728d4d8e2060180751e4cb3a698 /lib/Target/X86/PeepholeOptimizer.cpp | |
parent | 7200c6b82acb8401048a2bc8a423f23b48db6731 (diff) | |
download | llvm-6d2fdcfb8a922570d3a60540d36eb7804e7296f2.tar.gz llvm-6d2fdcfb8a922570d3a60540d36eb7804e7296f2.tar.bz2 llvm-6d2fdcfb8a922570d3a60540d36eb7804e7296f2.tar.xz |
The two address pass cannot handle two addr instructions where one incoming
value is a physreg and one is a virtreg. For this reason, disable copy folding
entirely for physregs. Also, use the new isMoveInstr target hook which gives us
folding of FP moves as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11700 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/PeepholeOptimizer.cpp')
-rw-r--r-- | lib/Target/X86/PeepholeOptimizer.cpp | 25 |
1 files changed, 16 insertions, 9 deletions
diff --git a/lib/Target/X86/PeepholeOptimizer.cpp b/lib/Target/X86/PeepholeOptimizer.cpp index 4d52b74d3f..1ceef0edc5 100644 --- a/lib/Target/X86/PeepholeOptimizer.cpp +++ b/lib/Target/X86/PeepholeOptimizer.cpp @@ -15,6 +15,8 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Target/TargetMachine.h" #include "Support/Statistic.h" #include "Support/STLExtras.h" @@ -23,6 +25,7 @@ using namespace llvm; namespace { Statistic<> NumPHOpts("x86-peephole", "Number of peephole optimization performed"); + Statistic<> NumPHMoves("x86-peephole", "Number of peephole moves folded"); struct PH : public MachineFunctionPass { virtual bool runOnMachineFunction(MachineFunction &MF); @@ -449,22 +452,26 @@ bool SSAPH::PeepholeOptimize(MachineBasicBlock &MBB, bool Changed = false; + const TargetInstrInfo &TII = MBB.getParent()->getTarget().getInstrInfo(); + // Scan the operands of this instruction. If any operands are // register-register copies, replace the operand with the source. for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) // Is this an SSA register use? - if (MachineInstr *DefInst = getDefiningInst(MI->getOperand(i))) + if (MachineInstr *DefInst = getDefiningInst(MI->getOperand(i))) { // If the operand is a vreg-vreg copy, it is always safe to replace the // source value with the input operand. - if (DefInst->getOpcode() == X86::MOVrr8 || - DefInst->getOpcode() == X86::MOVrr16 || - DefInst->getOpcode() == X86::MOVrr32) { - // Don't propagate physical registers into PHI nodes... - if (MI->getOpcode() != X86::PHI || - (DefInst->getOperand(1).isRegister() && - MRegisterInfo::isVirtualRegister(DefInst->getOperand(1).getReg()))) - Changed = Propagate(MI, i, DefInst, 1); + unsigned Source, Dest; + if (TII.isMoveInstr(*DefInst, Source, Dest)) { + // Don't propagate physical registers into any instructions. + if (DefInst->getOperand(1).isRegister() && + MRegisterInfo::isVirtualRegister(Source)) { + MI->getOperand(i).setReg(Source); + Changed = true; + ++NumPHMoves; + } } + } // Perform instruction specific optimizations. |