Remove uses of MachineOperand::isVirtualRegister

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11281 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 6 insertions, 3 deletions

diff --git a/lib/Target/X86/PeepholeOptimizer.cpp b/lib/Target/X86/PeepholeOptimizer.cpp
index 6d07ec502a..66508376cd 100644
--- a/lib/Target/X86/PeepholeOptimizer.cpp
+++ b/lib/Target/X86/PeepholeOptimizer.cpp
@@ -191,7 +191,8 @@ namespace {
           MachineInstr *MI = *I;
           for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
             MachineOperand &MO = MI->getOperand(i);
-            if (MO.isVirtualRegister() && MO.isDef() && !MO.isUse())
+            if (MO.isRegister() && MO.isDef() && !MO.isUse() &&
+                MRegisterInfo::isVirtualRegister(MO.getReg()))
               setDefinition(MO.getReg(), MI);
           }
         }
@@ -250,7 +251,8 @@ namespace {
     /// register, return the machine instruction defining it, otherwise, return
     /// null.
     MachineInstr *getDefiningInst(MachineOperand &MO) {
-      if (MO.isDef() || !MO.isVirtualRegister()) return 0;
+      if (MO.isDef() || !MO.isRegister() ||
+          !MRegisterInfo::isVirtualRegister(MO.getReg())) return 0;
       return UDC->getDefinition(MO.getReg());
     }
 
@@ -391,7 +393,8 @@ bool SSAPH::PeepholeOptimize(MachineBasicBlock &MBB,
           DefInst->getOpcode() == X86::MOVrr32) {
         // Don't propagate physical registers into PHI nodes...
         if (MI->getOpcode() != X86::PHI ||
-            DefInst->getOperand(1).isVirtualRegister())
+            (DefInst->getOperand(1).isRegister() &&
+             MRegisterInfo::isVirtualRegister(DefInst->getOperand(1).getReg())))
         Changed = Propagate(MI, i, DefInst, 1);
       }