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authorChris Lattner <sabre@nondot.org>2003-08-03 21:57:05 +0000
committerChris Lattner <sabre@nondot.org>2003-08-03 21:57:05 +0000
commit8d44ba8c5c2d66425caecb679727fe109d7e578d (patch)
tree449ec4305759d51bbda9ee6bc1522abff29d192c /lib/Target/X86/X86.h
parent113455be9d69f881165abafb6b6b0dd5b4b54aa8 (diff)
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Start using tablegen'd instruction enum list
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7542 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86.h')
-rw-r--r--lib/Target/X86/X86.h13
1 files changed, 3 insertions, 10 deletions
diff --git a/lib/Target/X86/X86.h b/lib/Target/X86/X86.h
index 9cb15c383c..61d3123ef6 100644
--- a/lib/Target/X86/X86.h
+++ b/lib/Target/X86/X86.h
@@ -47,15 +47,8 @@ Pass *createEmitX86CodeToMemory();
//
#include "X86GenRegisterNames.inc"
-/// X86 namespace - This namespace contains all of the register and opcode enums
-/// used by the X86 backend.
-///
-namespace X86 {
- // This defines a large number of symbolic names for X86 instruction opcodes.
- enum Opcode {
-#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS, IMPDEFS, IMPUSES) ENUM,
-#include "X86InstrInfo.def"
- };
-}
+// Defines symbolic names for the X86 instructions.
+//
+#include "X86GenInstrNames.inc"
#endif