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authorChris Lattner <sabre@nondot.org>2003-08-03 21:54:21 +0000
committerChris Lattner <sabre@nondot.org>2003-08-03 21:54:21 +0000
commit1cca5e3a29792c6927e337ba91e3b16c01c185ab (patch)
tree26e3730fbdfe0e69750b2b6d083a836a6ca58938 /lib/Target/X86/X86.td
parent5302e28adb1efa679d2cbdb3ca52cd9cd098f2dc (diff)
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Add new TableGen instruction definitions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7537 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86.td')
-rw-r--r--lib/Target/X86/X86.td11
1 files changed, 11 insertions, 0 deletions
diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td
index de2d619dd4..bb8dcb291c 100644
--- a/lib/Target/X86/X86.td
+++ b/lib/Target/X86/X86.td
@@ -19,7 +19,18 @@ include "X86RegisterInfo.td"
// Instruction Descriptions
//===----------------------------------------------------------------------===//
+include "X86InstrInfo.td"
+
def X86InstrInfo : InstrInfo {
+ set PHIInst = PHI;
+ set NOOPInst = NOOP;
+
+ // Define how we want to layout our TargetSpecific information field... This
+ // should be kept up-to-date with the fields in the X86InstrInfo.h file.
+ set TSFlagsFields = ["FormBits", "isVoid", "hasOpSizePrefix", "Prefix",
+ "TypeBits", "FPFormBits", "printImplicitUses", "Opcode"];
+ set TSFlagsShifts = [ 0, 5, 6, 7,
+ 11, 14, 17, 18];
}
def X86 : Target {