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| author | Andrew Lenharth <andrewl@lenharth.org> | 2008-03-01 13:37:02 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2008-03-01 13:37:02 +0000 |
| commit | ea7da50e5a7f291295c10d91fc3fdba76d339579 (patch) | |
| tree | d0b6e51981fee0a2df1431043fc037419cce4957 /lib/Target/X86/X86CodeEmitter.cpp | |
| parent | ec9a35a6f9143cfa325e0413cc297c48f627973a (diff) | |
| download | llvm-ea7da50e5a7f291295c10d91fc3fdba76d339579.tar.gz llvm-ea7da50e5a7f291295c10d91fc3fdba76d339579.tar.bz2 llvm-ea7da50e5a7f291295c10d91fc3fdba76d339579.tar.xz | |
Add lock prefix support to x86. Also add the instructions necessary for the atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47795 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86CodeEmitter.cpp')
| -rw-r--r-- | lib/Target/X86/X86CodeEmitter.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp index 894726cf35..522891c7cd 100644 --- a/lib/Target/X86/X86CodeEmitter.cpp +++ b/lib/Target/X86/X86CodeEmitter.cpp @@ -540,6 +540,9 @@ void Emitter::emitInstruction(const MachineInstr &MI, const TargetInstrDesc *Desc) { unsigned Opcode = Desc->Opcode; + // Emit the lock opcode prefix as needed. + if (Desc->TSFlags & X86II::LOCK) MCE.emitByte(0xF0); + // Emit the repeat opcode prefix as needed. if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3); |