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author | Andrew Trick <atrick@apple.com> | 2013-11-26 02:03:20 +0000 |
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committer | Andrew Trick <atrick@apple.com> | 2013-11-26 02:03:20 +0000 |
commit | 151ed664892bfd43560071034cb2fd8f74a11a61 (patch) | |
tree | 9836126e163b00d9d8200408fefa6994411a08fc /lib/Target/X86/X86ISelLowering.cpp | |
parent | 59ac92ab4bc96b8682bea7e45ec559b662c8c0ce (diff) | |
download | llvm-151ed664892bfd43560071034cb2fd8f74a11a61.tar.gz llvm-151ed664892bfd43560071034cb2fd8f74a11a61.tar.bz2 llvm-151ed664892bfd43560071034cb2fd8f74a11a61.tar.xz |
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195711 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86ISelLowering.cpp')
-rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index df2785c067..f4c926ec8b 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -17943,12 +17943,12 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, MachineFunction &MF = DAG.getMachineFunction(); bool OptForSize = MF.getFunction()->getAttributes(). hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize); - - // SHLD/SHRD instructions have lower register pressure, but on some - // platforms they have higher latency than the equivalent - // series of shifts/or that would otherwise be generated. + + // SHLD/SHRD instructions have lower register pressure, but on some + // platforms they have higher latency than the equivalent + // series of shifts/or that would otherwise be generated. // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions - // have higer latencies and we are not optimizing for size. + // have higher latencies and we are not optimizing for size. if (!OptForSize && Subtarget->isSHLDSlow()) return SDValue(); |