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authorNAKAMURA Takumi <geek4civic@gmail.com>2012-12-19 10:12:48 +0000
committerNAKAMURA Takumi <geek4civic@gmail.com>2012-12-19 10:12:48 +0000
commit16537418f4309ba0ab89f6b0dbadc77014ca671f (patch)
treef615ec1b77157aa188aa3c46f0d71ce6390d1464 /lib/Target/X86/X86ISelLowering.cpp
parent9c5ab9355e00686e120e12952908ea8ad981d776 (diff)
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X86ISelLowering.cpp: Fix warnings. [-Wlogical-op-parentheses]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170523 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86ISelLowering.cpp')
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index fee9d932e5..93ea3721fe 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -15934,8 +15934,8 @@ static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
// TODO: It is possible to support ZExt by zeroing the undef values
// during the shuffle phase or after the shuffle.
if (RegVT.isVector() && RegVT.isInteger() &&
- (Ext == ISD::EXTLOAD && Subtarget->hasSSSE3() ||
- Ext == ISD::SEXTLOAD && Subtarget->hasSSE41())){
+ ((Ext == ISD::EXTLOAD && Subtarget->hasSSSE3()) ||
+ (Ext == ISD::SEXTLOAD && Subtarget->hasSSE41()))){
assert(MemVT != RegVT && "Cannot extend to the same type");
assert(MemVT.isVector() && "Must load a vector from memory");