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| author | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2013-12-16 13:52:35 +0000 |
|---|---|---|
| committer | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2013-12-16 13:52:35 +0000 |
| commit | 376a81d8cef3546d9898b1b4c3439dbe557f88f7 (patch) | |
| tree | e86d3d0d315feea5bac20775e5ac8183afe9223e /lib/Target/X86/X86ISelLowering.h | |
| parent | 64f5838550435e3b7423f2c10631bad79461cadb (diff) | |
| download | llvm-376a81d8cef3546d9898b1b4c3439dbe557f88f7.tar.gz llvm-376a81d8cef3546d9898b1b4c3439dbe557f88f7.tar.bz2 llvm-376a81d8cef3546d9898b1b4c3439dbe557f88f7.tar.xz | |
AVX-512: Added legal type MVT::i1 and VK1 register for it.
Added scalar compare VCMPSS, VCMPSD.
Implemented LowerSELECT for scalar FP operations.
I replaced FSETCCss, FSETCCsd with one node type FSETCCs.
Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197384 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86ISelLowering.h')
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h index bc3dd608da..0b3495dc1b 100644 --- a/lib/Target/X86/X86ISelLowering.h +++ b/lib/Target/X86/X86ISelLowering.h @@ -94,6 +94,9 @@ namespace llvm { /// operand, usually produced by a CMP instruction. SETCC, + /// X86 Select + SELECT, + // Same as SETCC except it's materialized with a sbb and the value is all // one's or all zero's. SETCC_CARRY, // R = carry_bit ? ~0 : 0 @@ -101,7 +104,7 @@ namespace llvm { /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD. /// Operands are two FP values to compare; result is a mask of /// 0s or 1s. Generally DTRT for C/C++ with NaNs. - FSETCCss, FSETCCsd, + FSETCC, /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values, /// result in an integer GPR. Needs masking for scalar result. @@ -314,7 +317,6 @@ namespace llvm { // OR/AND test for masks KORTEST, - KTEST, // Several flavors of instructions with vector shuffle behaviors. PALIGNR, |