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author | Eli Friedman <eli.friedman@gmail.com> | 2011-09-07 18:48:32 +0000 |
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committer | Eli Friedman <eli.friedman@gmail.com> | 2011-09-07 18:48:32 +0000 |
commit | d5ccb0558fe986585fc56d208b35d0deec1912ff (patch) | |
tree | 9d78772483a0877ccfb3064ad6c7707403194389 /lib/Target/X86/X86InstrCompiler.td | |
parent | 90502888f222c10f351def6dafb8560411b680d3 (diff) | |
download | llvm-d5ccb0558fe986585fc56d208b35d0deec1912ff.tar.gz llvm-d5ccb0558fe986585fc56d208b35d0deec1912ff.tar.bz2 llvm-d5ccb0558fe986585fc56d208b35d0deec1912ff.tar.xz |
Fix atomic load and store on x86 to pass -verify-machineinstrs (and possibly fix some subtle bugs involving passes which check mayStore()).
This isn't exactly ideal, but it is good enough for the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139245 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrCompiler.td')
-rw-r--r-- | lib/Target/X86/X86InstrCompiler.td | 40 |
1 files changed, 26 insertions, 14 deletions
diff --git a/lib/Target/X86/X86InstrCompiler.td b/lib/Target/X86/X86InstrCompiler.td index 32c2842d62..3895b9f64f 100644 --- a/lib/Target/X86/X86InstrCompiler.td +++ b/lib/Target/X86/X86InstrCompiler.td @@ -741,6 +741,32 @@ def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val,i64mem:$ptr), TB, LOCK; } +def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src), + "#ACQUIRE_MOV PSEUDO!", + [(set GR8:$dst, (atomic_load_8 addr:$src))]>; +def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src), + "#ACQUIRE_MOV PSEUDO!", + [(set GR16:$dst, (atomic_load_16 addr:$src))]>; +def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src), + "#ACQUIRE_MOV PSEUDO!", + [(set GR32:$dst, (atomic_load_32 addr:$src))]>; +def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src), + "#ACQUIRE_MOV PSEUDO!", + [(set GR64:$dst, (atomic_load_64 addr:$src))]>; + +def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src), + "#RELEASE_MOV PSEUDO!", + [(atomic_store_8 addr:$dst, GR8 :$src)]>; +def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src), + "#RELEASE_MOV PSEUDO!", + [(atomic_store_16 addr:$dst, GR16:$src)]>; +def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src), + "#RELEASE_MOV PSEUDO!", + [(atomic_store_32 addr:$dst, GR32:$src)]>; +def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src), + "#RELEASE_MOV PSEUDO!", + [(atomic_store_64 addr:$dst, GR64:$src)]>; + //===----------------------------------------------------------------------===// // Conditional Move Pseudo Instructions. //===----------------------------------------------------------------------===// @@ -1709,17 +1735,3 @@ def : Pat<(and GR64:$src1, i64immSExt8:$src2), (AND64ri8 GR64:$src1, i64immSExt8:$src2)>; def : Pat<(and GR64:$src1, i64immSExt32:$src2), (AND64ri32 GR64:$src1, i64immSExt32:$src2)>; - -def : Pat<(atomic_load_8 addr:$src), (MOV8rm addr:$src)>; -def : Pat<(atomic_load_16 addr:$src), (MOV16rm addr:$src)>; -def : Pat<(atomic_load_32 addr:$src), (MOV32rm addr:$src)>; -def : Pat<(atomic_load_64 addr:$src), (MOV64rm addr:$src)>; - -def : Pat<(atomic_store_8 addr:$ptr, GR8:$val), - (MOV8mr addr:$ptr, GR8:$val)>; -def : Pat<(atomic_store_16 addr:$ptr, GR16:$val), - (MOV16mr addr:$ptr, GR16:$val)>; -def : Pat<(atomic_store_32 addr:$ptr, GR32:$val), - (MOV32mr addr:$ptr, GR32:$val)>; -def : Pat<(atomic_store_64 addr:$ptr, GR64:$val), - (MOV64mr addr:$ptr, GR64:$val)>; |