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| author | Craig Topper <craig.topper@gmail.com> | 2012-09-19 06:06:34 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2012-09-19 06:06:34 +0000 |
| commit | cbf3daee0bb3a4b8e532125a50567cc39407607e (patch) | |
| tree | 07fdfbff06015603e0d471722d569bc8a7dbefa0 /lib/Target/X86/X86InstrFMA.td | |
| parent | 67076a91cf5572ae75680b48f507a066e7ea36d4 (diff) | |
| download | llvm-cbf3daee0bb3a4b8e532125a50567cc39407607e.tar.gz llvm-cbf3daee0bb3a4b8e532125a50567cc39407607e.tar.bz2 llvm-cbf3daee0bb3a4b8e532125a50567cc39407607e.tar.xz | |
Add explicit VEX_L tags to all 256-bit instructions. This will allow us to remove code from the code emitters that examined operands to set the L-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164202 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrFMA.td')
| -rw-r--r-- | lib/Target/X86/X86InstrFMA.td | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/lib/Target/X86/X86InstrFMA.td b/lib/Target/X86/X86InstrFMA.td index 56638002d8..959d91a9ab 100644 --- a/lib/Target/X86/X86InstrFMA.td +++ b/lib/Target/X86/X86InstrFMA.td @@ -42,7 +42,7 @@ multiclass fma3p_rm<bits<8> opc, string OpcodeStr, !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), [(set VR256:$dst, (OpVT256 (Op VR256:$src2, VR256:$src1, - VR256:$src3)))]>; + VR256:$src3)))]>, VEX_L; let mayLoad = 1 in def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst), @@ -51,7 +51,7 @@ multiclass fma3p_rm<bits<8> opc, string OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), [(set VR256:$dst, (OpVT256 (Op VR256:$src2, VR256:$src1, - (MemFrag256 addr:$src3))))]>; + (MemFrag256 addr:$src3))))]>, VEX_L; } } // Constraints = "$src1 = $dst" @@ -280,19 +280,19 @@ multiclass fma4p<bits<8> opc, string OpcodeStr, SDNode OpNode, "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), [(set VR256:$dst, (OpVT256 (OpNode VR256:$src1, VR256:$src2, VR256:$src3)))]>, - VEX_W, MemOp4; + VEX_W, MemOp4, VEX_L; def rmY : FMA4<opc, MRMSrcMem, (outs VR256:$dst), (ins VR256:$src1, VR256:$src2, f256mem:$src3), !strconcat(OpcodeStr, "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), [(set VR256:$dst, (OpNode VR256:$src1, VR256:$src2, - (ld_frag256 addr:$src3)))]>, VEX_W, MemOp4; + (ld_frag256 addr:$src3)))]>, VEX_W, MemOp4, VEX_L; def mrY : FMA4<opc, MRMSrcMem, (outs VR256:$dst), (ins VR256:$src1, f256mem:$src2, VR256:$src3), !strconcat(OpcodeStr, "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), - [(set VR256:$dst, - (OpNode VR256:$src1, (ld_frag256 addr:$src2), VR256:$src3))]>; + [(set VR256:$dst, (OpNode VR256:$src1, + (ld_frag256 addr:$src2), VR256:$src3))]>, VEX_L; // For disassembler let isCodeGenOnly = 1 in { def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst), @@ -302,7 +302,8 @@ let isCodeGenOnly = 1 in { def rrY_REV : FMA4<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src1, VR256:$src2, VR256:$src3), !strconcat(OpcodeStr, - "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>; + "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>, + VEX_L; } // isCodeGenOnly = 1 } |