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author | Sean Callanan <scallanan@apple.com> | 2009-09-16 01:13:52 +0000 |
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committer | Sean Callanan <scallanan@apple.com> | 2009-09-16 01:13:52 +0000 |
commit | 5ab9403bc2c3f1f7fc4044ff4a7c394044a1c9e9 (patch) | |
tree | f1a8adbdb3baf2731687e30f011f20fe27738067 /lib/Target/X86/X86InstrFPStack.td | |
parent | 25d812bd7d1f58f2ba1b598b1425a2e146e27381 (diff) | |
download | llvm-5ab9403bc2c3f1f7fc4044ff4a7c394044a1c9e9.tar.gz llvm-5ab9403bc2c3f1f7fc4044ff4a7c394044a1c9e9.tar.bz2 llvm-5ab9403bc2c3f1f7fc4044ff4a7c394044a1c9e9.tar.xz |
Added a variety of floating-point and SSE instructions.
All of these do not have patterns (they're for the
disassembler).
Many of the floating-point instructions will probably
be rolled into definitions that have patterns, and may
eventually be superseded by mdefs. So I put them
together and left a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81979 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrFPStack.td')
-rw-r--r-- | lib/Target/X86/X86InstrFPStack.td | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/lib/Target/X86/X86InstrFPStack.td b/lib/Target/X86/X86InstrFPStack.td index bc7def457c..aeceec9672 100644 --- a/lib/Target/X86/X86InstrFPStack.td +++ b/lib/Target/X86/X86InstrFPStack.td @@ -303,6 +303,36 @@ def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>; } def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9; +// Versions of FP instructions that take a single memory operand. Added for the +// disassembler; remove as they are included with patterns elsewhere. +def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom\t$src">; +def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp\t$src">; + +def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">; +def FSTENVm : FPI<0xD9, MRM6m, (outs f32mem:$dst), (ins), "fstenv\t$dst">; + +def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">; +def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">; + +def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom\t$src">; +def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp\t$src">; + +def FLD64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld\t$src">; +def FISTTP32m: FPI<0xDD, MRM1m, (outs i32mem:$dst), (ins), "fisttp{l}\t$dst">; +def FST64m : FPI<0xDD, MRM2m, (outs f64mem:$dst), (ins), "fst\t$dst">; +def FSTP64m : FPI<0xDD, MRM3m, (outs f64mem:$dst), (ins), "fld\t$dst">; +def FRSTORm : FPI<0xDD, MRM4m, (outs f32mem:$dst), (ins), "frstor\t$dst">; +def FSAVEm : FPI<0xDD, MRM6m, (outs f32mem:$dst), (ins), "fsave\t$dst">; +def FSTSWm : FPI<0xDD, MRM7m, (outs f32mem:$dst), (ins), "fstsw\t$dst">; + +def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{w}\t$src">; +def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{w}\t$src">; + +def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f32mem:$src), "fbld\t$src">; +def FILD64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{q}\t$src">; +def FBSTPm : FPI<0xDF, MRM6m, (outs f32mem:$dst), (ins), "fbstp\t$dst">; +def FISTP64m : FPI<0xDF, MRM7m, (outs i64mem:$dst), (ins), "fistp{q}\t$dst">; + // Floating point cmovs. multiclass FPCMov<PatLeaf cc> { def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), |