Remove special FP opcode maps and instead add enough MRM_XX formats to handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201649 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 27 insertions, 53 deletions

diff --git a/lib/Target/X86/X86InstrFormats.td b/lib/Target/X86/X86InstrFormats.td
index bd210040f4..0f6533dcea 100644
--- a/lib/Target/X86/X86InstrFormats.td
+++ b/lib/Target/X86/X86InstrFormats.td
@@ -14,8 +14,8 @@
 // Format specifies the encoding used by the instruction.  This is part of the
 // ad-hoc solution used to emit machine instruction encodings by our machine
 // code emitter.
-class Format<bits<6> val> {
-  bits<6> Value = val;
+class Format<bits<7> val> {
+  bits<7> Value = val;
 }
 
 def Pseudo     : Format<0>; def RawFrm     : Format<1>;
@@ -33,33 +33,23 @@ def MRM6r  : Format<22>; def MRM7r  : Format<23>;
 def MRM0m  : Format<24>; def MRM1m  : Format<25>; def MRM2m  : Format<26>;
 def MRM3m  : Format<27>; def MRM4m  : Format<28>; def MRM5m  : Format<29>;
 def MRM6m  : Format<30>; def MRM7m  : Format<31>;
-def MRM_C0 : Format<32>;
-def MRM_C1 : Format<33>;
-def MRM_C2 : Format<34>;
-def MRM_C3 : Format<35>;
-def MRM_C4 : Format<36>;
-def MRM_C8 : Format<37>;
-def MRM_C9 : Format<38>;
-def MRM_CA : Format<39>;
-def MRM_CB : Format<40>;
-def MRM_D0 : Format<41>;
-def MRM_D1 : Format<42>;
-def MRM_D4 : Format<43>;
-def MRM_D5 : Format<44>;
-def MRM_D6 : Format<45>;
-def MRM_D8 : Format<46>;
-def MRM_D9 : Format<47>;
-def MRM_DA : Format<48>;
-def MRM_DB : Format<49>;
-def MRM_DC : Format<50>;
-def MRM_DD : Format<51>;
-def MRM_DE : Format<52>;
-def MRM_DF : Format<53>;
-def MRM_E0 : Format<54>;
-def MRM_E8 : Format<55>;
-def MRM_F0 : Format<56>;
-def MRM_F8 : Format<57>;
-def MRM_F9 : Format<58>;
+def MRM_C0 : Format<32>; def MRM_C1 : Format<33>; def MRM_C2 : Format<34>;
+def MRM_C3 : Format<35>; def MRM_C4 : Format<36>; def MRM_C8 : Format<37>;
+def MRM_C9 : Format<38>; def MRM_CA : Format<39>; def MRM_CB : Format<40>;
+def MRM_D0 : Format<41>; def MRM_D1 : Format<42>; def MRM_D4 : Format<43>;
+def MRM_D5 : Format<44>; def MRM_D6 : Format<45>; def MRM_D8 : Format<46>;
+def MRM_D9 : Format<47>; def MRM_DA : Format<48>; def MRM_DB : Format<49>;
+def MRM_DC : Format<50>; def MRM_DD : Format<51>; def MRM_DE : Format<52>;
+def MRM_DF : Format<53>; def MRM_E0 : Format<54>; def MRM_E1 : Format<55>;
+def MRM_E2 : Format<56>; def MRM_E3 : Format<57>; def MRM_E4 : Format<58>;
+def MRM_E5 : Format<59>; def MRM_E8 : Format<60>; def MRM_E9 : Format<61>;
+def MRM_EA : Format<62>; def MRM_EB : Format<63>; def MRM_EC : Format<64>;
+def MRM_ED : Format<65>; def MRM_EE : Format<66>; def MRM_F0 : Format<67>;
+def MRM_F1 : Format<68>; def MRM_F2 : Format<69>; def MRM_F3 : Format<70>;
+def MRM_F4 : Format<71>; def MRM_F5 : Format<72>; def MRM_F6 : Format<73>;
+def MRM_F7 : Format<74>; def MRM_F8 : Format<75>; def MRM_F9 : Format<76>;
+def MRM_FA : Format<77>; def MRM_FB : Format<78>; def MRM_FC : Format<79>;
+def MRM_FD : Format<80>; def MRM_FE : Format<81>; def MRM_FF : Format<82>;
 
 // ImmType - This specifies the immediate type used by an instruction. This is
 // part of the ad-hoc solution used to emit machine instruction encodings by our
@@ -126,8 +116,8 @@ def XS     : Prefix<3>;
 def XD     : Prefix<4>;
 
 // Class specifying the opcode map.
-class Map<bits<4> val> {
-  bits<4> Value = val;
+class Map<bits<3> val> {
+  bits<3> Value = val;
 }
 def OB   : Map<0>;
 def TB   : Map<1>;
@@ -136,14 +126,6 @@ def TA   : Map<3>;
 def XOP8 : Map<4>;
 def XOP9 : Map<5>;
 def XOPA : Map<6>;
-def D8   : Map<7>;
-def D9   : Map<8>;
-def DA   : Map<9>;
-def DB   : Map<10>;
-def DC   : Map<11>;
-def DD   : Map<12>;
-def DE   : Map<13>;
-def DF   : Map<14>;
 
 // Class specifying the encoding
 class Encoding<bits<2> val> {
@@ -171,14 +153,6 @@ class REX_W  { bit hasREX_WPrefix = 1; }
 class LOCK   { bit hasLockPrefix = 1; }
 class REP    { bit hasREPPrefix = 1; }
 class TB     { Map OpMap = TB; }
-class D8     { Map OpMap = D8; }
-class D9     { Map OpMap = D9; }
-class DA     { Map OpMap = DA; }
-class DB     { Map OpMap = DB; }
-class DC     { Map OpMap = DC; }
-class DD     { Map OpMap = DD; }
-class DE     { Map OpMap = DE; }
-class DF     { Map OpMap = DF; }
 class T8     { Map OpMap = T8; }
 class TA     { Map OpMap = TA; }
 class XOP8   { Map OpMap = XOP8; Prefix OpPrefix = PS; }
@@ -231,7 +205,7 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
 
   bits<8> Opcode = opcod;
   Format Form = f;
-  bits<6> FormBits = Form.Value;
+  bits<7> FormBits = Form.Value;
   ImmType ImmT = i;
 
   dag OutOperandList = outs;
@@ -281,11 +255,11 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
   bit hasEVEX_RC = 0;       // Explicitly specified rounding control in FP instruction.
 
   // TSFlags layout should be kept in sync with X86InstrInfo.h.
-  let TSFlags{5-0}   = FormBits;
-  let TSFlags{7-6}   = OpSize.Value;
-  let TSFlags{8}     = hasAdSizePrefix;
-  let TSFlags{11-9}  = OpPrefix.Value;
-  let TSFlags{15-12} = OpMap.Value;
+  let TSFlags{6-0}   = FormBits;
+  let TSFlags{8-7}   = OpSize.Value;
+  let TSFlags{9}     = hasAdSizePrefix;
+  let TSFlags{12-10} = OpPrefix.Value;
+  let TSFlags{15-13} = OpMap.Value;
   let TSFlags{16}    = hasREX_WPrefix;
   let TSFlags{20-17} = ImmT.Value;
   let TSFlags{23-21} = FPForm.Value;