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| author | Craig Topper <craig.topper@gmail.com> | 2012-12-29 16:44:25 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2012-12-29 16:44:25 +0000 |
| commit | 6d183e400720b703dc9dbe6c8a28b615441601a2 (patch) | |
| tree | 26fa06238c49006592f44eb6893a7b2ed94c8d6f /lib/Target/X86/X86InstrInfo.cpp | |
| parent | c20323a7588bc5ad327155fe09c2b51435c3ada2 (diff) | |
| download | llvm-6d183e400720b703dc9dbe6c8a28b615441601a2.tar.gz llvm-6d183e400720b703dc9dbe6c8a28b615441601a2.tar.bz2 llvm-6d183e400720b703dc9dbe6c8a28b615441601a2.tar.xz | |
Remove intrinsic specific instructions for SSE/SSE2/AVX floating point max/min instructions. Lower them to target specific nodes and use those patterns instead. This also allows them to be commuted if UnsafeFPMath is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171227 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrInfo.cpp')
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.cpp | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index bb81fa163f..f3ec067bdb 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -710,21 +710,13 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 }, { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 }, { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 }, - { X86::MAXPDrr_Int, X86::MAXPDrm_Int, TB_ALIGN_16 }, { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 }, - { X86::MAXPSrr_Int, X86::MAXPSrm_Int, TB_ALIGN_16 }, { X86::MAXSDrr, X86::MAXSDrm, 0 }, - { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 }, { X86::MAXSSrr, X86::MAXSSrm, 0 }, - { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 }, { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 }, - { X86::MINPDrr_Int, X86::MINPDrm_Int, TB_ALIGN_16 }, { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 }, - { X86::MINPSrr_Int, X86::MINPSrm_Int, TB_ALIGN_16 }, { X86::MINSDrr, X86::MINSDrm, 0 }, - { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 }, { X86::MINSSrr, X86::MINSSrm, 0 }, - { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 }, { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 }, { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 }, { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 }, @@ -896,21 +888,13 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 }, { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 }, { X86::VMAXPDrr, X86::VMAXPDrm, 0 }, - { X86::VMAXPDrr_Int, X86::VMAXPDrm_Int, 0 }, { X86::VMAXPSrr, X86::VMAXPSrm, 0 }, - { X86::VMAXPSrr_Int, X86::VMAXPSrm_Int, 0 }, { X86::VMAXSDrr, X86::VMAXSDrm, 0 }, - { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 }, { X86::VMAXSSrr, X86::VMAXSSrm, 0 }, - { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 }, { X86::VMINPDrr, X86::VMINPDrm, 0 }, - { X86::VMINPDrr_Int, X86::VMINPDrm_Int, 0 }, { X86::VMINPSrr, X86::VMINPSrm, 0 }, - { X86::VMINPSrr_Int, X86::VMINPSrm_Int, 0 }, { X86::VMINSDrr, X86::VMINSDrm, 0 }, - { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 }, { X86::VMINSSrr, X86::VMINSSrm, 0 }, - { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 }, { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 }, { X86::VMULPDrr, X86::VMULPDrm, 0 }, { X86::VMULPSrr, X86::VMULPSrm, 0 }, @@ -1037,13 +1021,9 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 }, { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 }, { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 }, - { X86::VMAXPDYrr_Int, X86::VMAXPDYrm_Int, 0 }, { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 }, - { X86::VMAXPSYrr_Int, X86::VMAXPSYrm_Int, 0 }, { X86::VMINPDYrr, X86::VMINPDYrm, 0 }, - { X86::VMINPDYrr_Int, X86::VMINPDYrm_Int, 0 }, { X86::VMINPSYrr, X86::VMINPSYrm, 0 }, - { X86::VMINPSYrr_Int, X86::VMINPSYrm_Int, 0 }, { X86::VMULPDYrr, X86::VMULPDYrm, 0 }, { X86::VMULPSYrr, X86::VMULPSYrm, 0 }, { X86::VORPDYrr, X86::VORPDYrm, 0 }, |