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| author | Bill Wendling <isanbard@gmail.com> | 2013-06-07 21:00:34 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2013-06-07 21:00:34 +0000 |
| commit | a5e5ba611f787f518fd3f7349343f8c4ae863fc2 (patch) | |
| tree | 7de9380d58b8555fcc8a89f014acdfe810fdba77 /lib/Target/X86/X86InstrInfo.cpp | |
| parent | 1ce4985e019fcb89c6d827ba6cd11e3c4365121b (diff) | |
| download | llvm-a5e5ba611f787f518fd3f7349343f8c4ae863fc2.tar.gz llvm-a5e5ba611f787f518fd3f7349343f8c4ae863fc2.tar.bz2 llvm-a5e5ba611f787f518fd3f7349343f8c4ae863fc2.tar.xz | |
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183571 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrInfo.cpp')
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 5ed8604a39..fca88b0de7 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -97,7 +97,7 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) (tm.getSubtarget<X86Subtarget>().is64Bit() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32)), - TM(tm), RI(tm, *this) { + TM(tm), RI(tm) { static const X86OpTblEntry OpTbl2Addr[] = { { X86::ADC32ri, X86::ADC32mi, 0 }, |