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authorManman Ren <mren@apple.com>2012-07-28 16:48:01 +0000
committerManman Ren <mren@apple.com>2012-07-28 16:48:01 +0000
commit0eb3edea9cb6819334173a7d288da85943201fe5 (patch)
tree77172a23d7618e5dbe447fc4b7536ba1a416deaf /lib/Target/X86/X86InstrInfo.h
parentcdfbcdeeede52de472ae8187c0fb4ed4a014c2a3 (diff)
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X86 Peephole: fold loads to the source register operand if possible.
Machine CSE and other optimizations can remove instructions so folding is possible at peephole while not possible at ISel. rdar://10554090 and rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160919 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrInfo.h')
-rw-r--r--lib/Target/X86/X86InstrInfo.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h
index ec9b2e619d..9205315653 100644
--- a/lib/Target/X86/X86InstrInfo.h
+++ b/lib/Target/X86/X86InstrInfo.h
@@ -387,6 +387,14 @@ public:
unsigned SrcReg2, int CmpMask, int CmpValue,
const MachineRegisterInfo *MRI) const;
+ /// optimizeLoadInstr - Try to remove the load by folding it to a register
+ /// operand at the use. We fold the load instructions if and only if the
+ /// def and use are in the same BB.
+ virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI,
+ const MachineRegisterInfo *MRI,
+ SmallSet<unsigned, 4> &FoldAsLoadDefRegs,
+ MachineInstr *&DefMI) const;
+
private:
MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
MachineFunction::iterator &MFI,