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authorElena Demikhovsky <elena.demikhovsky@intel.com>2014-01-01 15:12:34 +0000
committerElena Demikhovsky <elena.demikhovsky@intel.com>2014-01-01 15:12:34 +0000
commit3062a311ac2d1bf053e15cba621e168572c83a07 (patch)
tree2f5f667852e1418991b5bae856584a9fad38ac00 /lib/Target/X86/X86InstrInfo.td
parent979b2cd2bc97d4d6745f4959feb7e9706a9fb9f6 (diff)
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AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp
Printing rounding control. Enncoding for EVEX_RC (rounding control). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198277 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrInfo.td')
-rw-r--r--lib/Target/X86/X86InstrInfo.td4
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index f006b919f8..2fea6e1773 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -510,6 +510,10 @@ def GR32orGR64 : RegisterOperand<GR32> {
let ParserMatchClass = X86GR32orGR64AsmOperand;
}
+def AVX512RC : Operand<i32> {
+ let PrintMethod = "printRoundingControl";
+ let OperandType = "OPERAND_IMMEDIATE";
+}
// Sign-extended immediate classes. We don't need to define the full lattice
// here because there is no instruction with an ambiguity between ImmSExti64i32
// and ImmSExti32i8.