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| author | Alexey Volkov <avolkov.intel@gmail.com> | 2014-06-09 11:40:41 +0000 |
|---|---|---|
| committer | Alexey Volkov <avolkov.intel@gmail.com> | 2014-06-09 11:40:41 +0000 |
| commit | a2bc6951a028412e7af5e68aa369daa4611147b3 (patch) | |
| tree | e36b5b05d696ec346157589ad1e2ecb702e02123 /lib/Target/X86/X86InstrInfo.td | |
| parent | a8d18fe94687b65f136b7222c2cc998c2148e39c (diff) | |
| download | llvm-a2bc6951a028412e7af5e68aa369daa4611147b3.tar.gz llvm-a2bc6951a028412e7af5e68aa369daa4611147b3.tar.bz2 llvm-a2bc6951a028412e7af5e68aa369daa4611147b3.tar.xz | |
[X86] Use ADD/SUB instead of INC/DEC for Silvermont
According to Intel Software Optimization Manual
on Silvermont INC or DEC instructions require
an additional uop to merge the flags.
As a result, a branch instruction depending
on an INC or a DEC instruction incurs a 1 cycle penalty.
Differential Revision: http://reviews.llvm.org/D3990
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210466 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrInfo.td')
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 0d97669b22..5d34c326ac 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -795,6 +795,7 @@ def OptForSpeed : Predicate<"!OptForSize">; def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">; def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">; def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">; +def NotSlowIncDec : Predicate<"!Subtarget->slowIncDec()">; //===----------------------------------------------------------------------===// // X86 Instruction Format Definitions. |