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| author | Quentin Colombet <qcolombet@apple.com> | 2014-04-23 19:30:26 +0000 |
|---|---|---|
| committer | Quentin Colombet <qcolombet@apple.com> | 2014-04-23 19:30:26 +0000 |
| commit | 3ce58b3f602e503a156b0b0a3178b65a5023d9be (patch) | |
| tree | b2a2842739636d22a6a140dc116b5bcdbacb0a2f /lib/Target/X86/X86InstrSSE.td | |
| parent | d25fec6309f17cbce39c4e56d1ada5d8fc0f1862 (diff) | |
| download | llvm-3ce58b3f602e503a156b0b0a3178b65a5023d9be.tar.gz llvm-3ce58b3f602e503a156b0b0a3178b65a5023d9be.tar.bz2 llvm-3ce58b3f602e503a156b0b0a3178b65a5023d9be.tar.xz | |
[X86] Fix missing/wrong scheduling model found by code inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207014 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrSSE.td')
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 8229b2f7c6..3b0cc6bff2 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -7407,6 +7407,7 @@ let Predicates = [UseSSE41] in { } +let SchedRW = [WriteLoad] in { let Predicates = [HasAVX] in def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}", @@ -7420,6 +7421,7 @@ def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src), def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), "movntdqa\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>; +} // SchedRW //===----------------------------------------------------------------------===// // SSE4.2 - Compare Instructions |