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| author | Craig Topper <craig.topper@gmail.com> | 2014-02-02 09:25:09 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2014-02-02 09:25:09 +0000 |
| commit | 6b6dfa5c5a4d17a0425fb391206a6cd806e5ba7d (patch) | |
| tree | eb3508cb9c2457397ed1f1428899f3cf9704422f /lib/Target/X86/X86InstrSSE.td | |
| parent | 3c53b6f1ec476f881a701bda6439b615caf03217 (diff) | |
| download | llvm-6b6dfa5c5a4d17a0425fb391206a6cd806e5ba7d.tar.gz llvm-6b6dfa5c5a4d17a0425fb391206a6cd806e5ba7d.tar.bz2 llvm-6b6dfa5c5a4d17a0425fb391206a6cd806e5ba7d.tar.xz | |
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200626 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrSSE.td')
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 2a7688e878..af1352352c 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -6789,11 +6789,11 @@ let Defs = [EFLAGS], Predicates = [HasPOPCNT] in { "popcnt{w}\t{$src, $dst|$dst, $src}", [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)], IIC_SSE_POPCNT_RR>, - OpSize, XS; + OpSize16, XS; def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), "popcnt{w}\t{$src, $dst|$dst, $src}", [(set GR16:$dst, (ctpop (loadi16 addr:$src))), - (implicit EFLAGS)], IIC_SSE_POPCNT_RM>, OpSize, XS; + (implicit EFLAGS)], IIC_SSE_POPCNT_RM>, OpSize16, XS; def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), "popcnt{l}\t{$src, $dst|$dst, $src}", @@ -7478,13 +7478,13 @@ let Constraints = "$src1 = $dst" in { def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8, int_x86_sse42_crc32_32_8>; def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem, - int_x86_sse42_crc32_32_16>, OpSize; + int_x86_sse42_crc32_32_16>, OpSize16; def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16, - int_x86_sse42_crc32_32_16>, OpSize; + int_x86_sse42_crc32_32_16>, OpSize16; def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem, - int_x86_sse42_crc32_32_32>, OpSize16; + int_x86_sse42_crc32_32_32>, OpSize32; def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32, - int_x86_sse42_crc32_32_32>, OpSize16; + int_x86_sse42_crc32_32_32>, OpSize32; def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem, int_x86_sse42_crc32_64_64>, REX_W; def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64, |