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authorChad Rosier <mcrosier@apple.com>2013-05-29 20:42:21 +0000
committerChad Rosier <mcrosier@apple.com>2013-05-29 20:42:21 +0000
commit8ed5506e854ed1e98b6547a976719a867a968106 (patch)
tree7becaacdf0788458d0566054ebed748525e4e877 /lib/Target/X86/X86RegisterInfo.cpp
parent745825f582c866ae8bf605183d00772510d252c4 (diff)
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Don't assume the registers will be enumerated sequentially.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182879 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86RegisterInfo.cpp')
-rw-r--r--lib/Target/X86/X86RegisterInfo.cpp7
1 files changed, 5 insertions, 2 deletions
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 8dbc972a85..755afc3f1e 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -373,8 +373,11 @@ BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
Reserved.set(*AI);
// XMM8, XMM9, ...
- assert(X86::XMM15 == X86::XMM8+7);
- for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
+ static const uint16_t XMMReg[] = {
+ X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11,
+ X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15
+ };
+ for (MCRegAliasIterator AI(XMMReg[n], this, true); AI.isValid(); ++AI)
Reserved.set(*AI);
}
}