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| author | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2013-12-16 13:52:35 +0000 |
|---|---|---|
| committer | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2013-12-16 13:52:35 +0000 |
| commit | 376a81d8cef3546d9898b1b4c3439dbe557f88f7 (patch) | |
| tree | e86d3d0d315feea5bac20775e5ac8183afe9223e /lib/Target/X86/X86RegisterInfo.td | |
| parent | 64f5838550435e3b7423f2c10631bad79461cadb (diff) | |
| download | llvm-376a81d8cef3546d9898b1b4c3439dbe557f88f7.tar.gz llvm-376a81d8cef3546d9898b1b4c3439dbe557f88f7.tar.bz2 llvm-376a81d8cef3546d9898b1b4c3439dbe557f88f7.tar.xz | |
AVX-512: Added legal type MVT::i1 and VK1 register for it.
Added scalar compare VCMPSS, VCMPSD.
Implemented LowerSELECT for scalar FP operations.
I replaced FSETCCss, FSETCCsd with one node type FSETCCs.
Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197384 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86RegisterInfo.td')
| -rw-r--r-- | lib/Target/X86/X86RegisterInfo.td | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td index b8027283cc..8d79e13b1d 100644 --- a/lib/Target/X86/X86RegisterInfo.td +++ b/lib/Target/X86/X86RegisterInfo.td @@ -463,9 +463,11 @@ def VR128X : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], def VR256X : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 256, (sequence "YMM%u", 0, 31)>; +def VK1 : RegisterClass<"X86", [i1], 1, (sequence "K%u", 0, 7)>; def VK8 : RegisterClass<"X86", [v8i1], 8, (sequence "K%u", 0, 7)>; def VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)>; +def VK1WM : RegisterClass<"X86", [i1], 1, (sub VK1, K0)>; def VK8WM : RegisterClass<"X86", [v8i1], 8, (sub VK8, K0)>; def VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)>; |