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authorBruno Cardoso Lopes <bruno.cardoso@gmail.com>2010-07-24 00:06:39 +0000
committerBruno Cardoso Lopes <bruno.cardoso@gmail.com>2010-07-24 00:06:39 +0000
commit3c8e1bee6399e829eda801a32158c1f52d2733ad (patch)
tree005849e58183f7cfce81b14de865a4d253339d27 /lib/Target/X86/X86RegisterInfo.td
parentc2723a57f35dd69bd261faaa71ee7aa05f40a87d (diff)
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Support x86 "eiz" and "riz" pseudo index registers in the assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109295 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86RegisterInfo.td')
-rw-r--r--lib/Target/X86/X86RegisterInfo.td4
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td
index 6251b3c10f..176e87812d 100644
--- a/lib/Target/X86/X86RegisterInfo.td
+++ b/lib/Target/X86/X86RegisterInfo.td
@@ -241,6 +241,10 @@ let Namespace = "X86" in {
def CR6 : Register<"cr6">;
def CR7 : Register<"cr7">;
def CR8 : Register<"cr8">;
+
+ // Pseudo index registers
+ def EIZ : Register<"eiz">;
+ def RIZ : Register<"riz">;
}