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| author | Dan Gohman <gohman@apple.com> | 2009-04-27 16:41:36 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2009-04-27 16:41:36 +0000 |
| commit | 4af325d1b4b811277365a20aa6cfc7f719625198 (patch) | |
| tree | 8add8ebc471fac01fe71b9aac18ae549aa249cf8 /lib/Target/X86/X86RegisterInfo.td | |
| parent | 6241762c5a8f5e22679ffcd7a592e405e279f0a9 (diff) | |
| download | llvm-4af325d1b4b811277365a20aa6cfc7f719625198.tar.gz llvm-4af325d1b4b811277365a20aa6cfc7f719625198.tar.bz2 llvm-4af325d1b4b811277365a20aa6cfc7f719625198.tar.xz | |
Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use these
to precisely describe the h-register subreg register classes.
Thanks to Jakob Stoklund Olesen for spotting this and for the
initial patch!
Also, make getStoreRegOpcode and getLoadRegOpcode aware of the
needs of h registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70211 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86RegisterInfo.td')
| -rw-r--r-- | lib/Target/X86/X86RegisterInfo.td | 21 |
1 files changed, 12 insertions, 9 deletions
diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td index 773cba3ee0..d552cb3ab8 100644 --- a/lib/Target/X86/X86RegisterInfo.td +++ b/lib/Target/X86/X86RegisterInfo.td @@ -461,21 +461,24 @@ def GR64 : RegisterClass<"X86", [i64], 64, } -// GR8_ABCD, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of GR8, GR16, GR32, -// and GR64 which contain just the "a" "b", "c", and "d" registers. On x86-32, -// GR16_ABCD and GR32_ABCD are classes for registers that support 8-bit subreg -// operations. On x86-64, GR16_ABCD, GR32_ABCD, and GR64_ABCD are classes for -// registers that support 8-bit h-register operations. -def GR8_ABCD : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL]> { +// GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of +// GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d" +// registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers +// that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD, +// and GR64_ABCD are classes for registers that support 8-bit h-register +// operations. +def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL]> { +} +def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, [AH, CH, DH, BH]> { } def GR16_ABCD : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> { - let SubRegClassList = [GR8_ABCD, GR8_ABCD]; + let SubRegClassList = [GR8_ABCD_L, GR8_ABCD_H]; } def GR32_ABCD : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> { - let SubRegClassList = [GR8_ABCD, GR8_ABCD, GR16_ABCD]; + let SubRegClassList = [GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD]; } def GR64_ABCD : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RBX]> { - let SubRegClassList = [GR8_ABCD, GR8_ABCD, GR16_ABCD, GR32_ABCD]; + let SubRegClassList = [GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD]; } // GR8_NOREX, GR16_NOREX, GR32_NOREX, GR64_NOREX - Subclasses of |