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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2013-03-19 21:16:56 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2013-03-19 21:16:56 +0000 |
| commit | f36a4afaaee1885a14c1b9d58f61b2bd26a75e88 (patch) | |
| tree | 33131f7230d8a84429a4566895e71bbe2df11d1b /lib/Target/X86/X86Schedule.td | |
| parent | 0f7ccd279dc65682899a6cdb112068f512bc0246 (diff) | |
| download | llvm-f36a4afaaee1885a14c1b9d58f61b2bd26a75e88.tar.gz llvm-f36a4afaaee1885a14c1b9d58f61b2bd26a75e88.tar.bz2 llvm-f36a4afaaee1885a14c1b9d58f61b2bd26a75e88.tar.xz | |
Annotate X86InstrCompiler.td with SchedRW lists.
Add a new WriteZero SchedWrite type for the common dependency-breaking
instructions that clear a register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177442 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86Schedule.td')
| -rw-r--r-- | lib/Target/X86/X86Schedule.td | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/X86/X86Schedule.td b/lib/Target/X86/X86Schedule.td index da0ca7d28e..dec3f43bd7 100644 --- a/lib/Target/X86/X86Schedule.td +++ b/lib/Target/X86/X86Schedule.td @@ -53,6 +53,10 @@ def WriteLoad : SchedWrite; def WriteStore : SchedWrite; def WriteMove : SchedWrite; +// Idioms that clear a register, like xorps %xmm0, %xmm0. +// These can often bypass execution ports completely. +def WriteZero : SchedWrite; + // Branches don't produce values, so they have no latency, but they still // consume resources. Indirect branches can fold loads. defm WriteJump : X86SchedWritePair; |