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| author | Evan Cheng <evan.cheng@apple.com> | 2011-11-16 08:38:26 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2011-11-16 08:38:26 +0000 |
| commit | b95fc31aa2e5a0a0b9ee1909d1cb949577c5aa16 (patch) | |
| tree | a891fa0a8cb7d5f75446fc0f0346eb55b18a715c /lib/Target/X86/X86TargetMachine.h | |
| parent | f1b41dd38d2b2713e3870f384525b020bbac05f6 (diff) | |
| download | llvm-b95fc31aa2e5a0a0b9ee1909d1cb949577c5aa16.tar.gz llvm-b95fc31aa2e5a0a0b9ee1909d1cb949577c5aa16.tar.bz2 llvm-b95fc31aa2e5a0a0b9ee1909d1cb949577c5aa16.tar.xz | |
Sink codegen optimization level into MCCodeGenInfo along side relocation model
and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144788 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86TargetMachine.h')
| -rw-r--r-- | lib/Target/X86/X86TargetMachine.h | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/lib/Target/X86/X86TargetMachine.h b/lib/Target/X86/X86TargetMachine.h index d1569aa9d7..64be4585cd 100644 --- a/lib/Target/X86/X86TargetMachine.h +++ b/lib/Target/X86/X86TargetMachine.h @@ -40,6 +40,7 @@ public: X86TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL, bool is64Bit); virtual const X86InstrInfo *getInstrInfo() const { @@ -66,11 +67,11 @@ public: } // Set up the pass pipeline. - virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel); - virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel); - virtual bool addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel); - virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel); - virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, + virtual bool addInstSelector(PassManagerBase &PM); + virtual bool addPreRegAlloc(PassManagerBase &PM); + virtual bool addPostRegAlloc(PassManagerBase &PM); + virtual bool addPreEmitPass(PassManagerBase &PM); + virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE); }; @@ -85,7 +86,8 @@ class X86_32TargetMachine : public X86TargetMachine { public: X86_32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM, CodeModel::Model CM); + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL); virtual const TargetData *getTargetData() const { return &DataLayout; } virtual const X86TargetLowering *getTargetLowering() const { return &TLInfo; @@ -112,7 +114,8 @@ class X86_64TargetMachine : public X86TargetMachine { public: X86_64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM, CodeModel::Model CM); + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL); virtual const TargetData *getTargetData() const { return &DataLayout; } virtual const X86TargetLowering *getTargetLowering() const { return &TLInfo; |