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| author | Duncan Sands <baldrick@free.fr> | 2011-09-17 16:49:39 +0000 |
|---|---|---|
| committer | Duncan Sands <baldrick@free.fr> | 2011-09-17 16:49:39 +0000 |
| commit | 6bcd2196e5febb97efe188d0d6de403c577d96fc (patch) | |
| tree | b147a99b1f7f3b65365ba8535f8466ab53f5d766 /lib/Target/X86 | |
| parent | 2c693dc1261d8b8d92b5c96cf00ec873dde86bb2 (diff) | |
| download | llvm-6bcd2196e5febb97efe188d0d6de403c577d96fc.tar.gz llvm-6bcd2196e5febb97efe188d0d6de403c577d96fc.tar.bz2 llvm-6bcd2196e5febb97efe188d0d6de403c577d96fc.tar.xz | |
Synthesize x86 max/min instructions also for vectors (i.e. produce
maxps and maxpd). This broke the sse41-blend.ll testcase by causing
maxpd to be produced rather than a cmp+blend pair, which is the reason
I tweaked it. Gives a small speedup on doduc with dragonegg when the
GCC vectorizer is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139986 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86')
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index d279e04729..42193c41cb 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -1129,6 +1129,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) setTargetDAGCombine(ISD::VECTOR_SHUFFLE); setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); setTargetDAGCombine(ISD::BUILD_VECTOR); + setTargetDAGCombine(ISD::VSELECT); setTargetDAGCombine(ISD::SELECT); setTargetDAGCombine(ISD::SHL); setTargetDAGCombine(ISD::SRA); @@ -12551,7 +12552,8 @@ static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, return SDValue(); } -/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. +/// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT +/// nodes. static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget) { DebugLoc DL = N->getDebugLoc(); @@ -12564,9 +12566,9 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, // instructions match the semantics of the common C idiom x<y?x:y but not // x<=y?x:y, because of how they handle negative zero (which can be // ignored in unsafe-math mode). - if (Subtarget->hasXMMInt() && - (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) && - Cond.getOpcode() == ISD::SETCC) { + if (Subtarget->hasXMMInt() && Cond.getOpcode() == ISD::SETCC && + (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64 || + LHS.getValueType() == MVT::v4f32 || LHS.getValueType() == MVT::v2f64)) { ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); unsigned Opcode = 0; @@ -13871,6 +13873,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, default: break; case ISD::EXTRACT_VECTOR_ELT: return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this); + case ISD::VSELECT: case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); case ISD::ADD: return OptimizeConditionalInDecrement(N, DAG); |