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| author | Adam Nemet <anemet@apple.com> | 2014-06-24 01:42:32 +0000 |
|---|---|---|
| committer | Adam Nemet <anemet@apple.com> | 2014-06-24 01:42:32 +0000 |
| commit | f36c3de849d4dacbdfd79c4f4178163e09b65efa (patch) | |
| tree | da8852b563a6a622e264ea4c05cdd66b2f7402df /lib/Target/X86 | |
| parent | 68cda26497ec5cc9471f2f5ab3fa7176ad46a00a (diff) | |
| download | llvm-f36c3de849d4dacbdfd79c4f4178163e09b65efa.tar.gz llvm-f36c3de849d4dacbdfd79c4f4178163e09b65efa.tar.bz2 llvm-f36c3de849d4dacbdfd79c4f4178163e09b65efa.tar.xz | |
[Disasm][AVX512] Implement decoding of top bit for non-destructive reg fields
V' bit in the P2 byte of the EVEX prefix provides the top bit of the NDD and
NDS register fields. This was simply not used in the decoder until now.
Fixes <rdar://problem/17402661>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211565 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86')
| -rw-r--r-- | lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp b/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp index 804606d917..55587d462f 100644 --- a/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp +++ b/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp @@ -1620,7 +1620,8 @@ static int readVVVV(struct InternalInstruction* insn) { int vvvv; if (insn->vectorExtensionType == TYPE_EVEX) - vvvv = vvvvFromEVEX3of4(insn->vectorExtensionPrefix[2]); + vvvv = (v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4 | + vvvvFromEVEX3of4(insn->vectorExtensionPrefix[2])); else if (insn->vectorExtensionType == TYPE_VEX_3B) vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]); else if (insn->vectorExtensionType == TYPE_VEX_2B) |