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author | Richard Osborne <richard@xmos.com> | 2008-11-07 10:59:00 +0000 |
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committer | Richard Osborne <richard@xmos.com> | 2008-11-07 10:59:00 +0000 |
commit | b25baef26f03b9909b65dd5f762b38f93000445d (patch) | |
tree | f03bc8e40b55feab99b0f32e4428d215fa45f988 /lib/Target/XCore/XCore.td | |
parent | 4df60f5491ff35c8a48c2cf14e18a33c9793b3bb (diff) | |
download | llvm-b25baef26f03b9909b65dd5f762b38f93000445d.tar.gz llvm-b25baef26f03b9909b65dd5f762b38f93000445d.tar.bz2 llvm-b25baef26f03b9909b65dd5f762b38f93000445d.tar.xz |
Add XCore backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58838 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore/XCore.td')
-rw-r--r-- | lib/Target/XCore/XCore.td | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/lib/Target/XCore/XCore.td b/lib/Target/XCore/XCore.td new file mode 100644 index 0000000000..39c4226b61 --- /dev/null +++ b/lib/Target/XCore/XCore.td @@ -0,0 +1,62 @@ +//===- XCore.td - Describe the XCore Target Machine --------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Target-independent interfaces which we are implementing +//===----------------------------------------------------------------------===// + +include "../Target.td" + +//===----------------------------------------------------------------------===// +// Descriptions +//===----------------------------------------------------------------------===// + +include "XCoreRegisterInfo.td" +include "XCoreInstrInfo.td" +include "XCoreCallingConv.td" + +def XCoreInstrInfo : InstrInfo { + let TSFlagsFields = []; + let TSFlagsShifts = []; +} + +//===----------------------------------------------------------------------===// +// XCore Subtarget features. +//===----------------------------------------------------------------------===// + +def FeatureXS1A + : SubtargetFeature<"xs1a", "IsXS1A", "true", + "Enable XS1A instructions">; + +def FeatureXS1B + : SubtargetFeature<"xs1b", "IsXS1B", "true", + "Enable XS1B instructions">; + +//===----------------------------------------------------------------------===// +// XCore processors supported. +//===----------------------------------------------------------------------===// + +class Proc<string Name, list<SubtargetFeature> Features> + : Processor<Name, NoItineraries, Features>; + +def : Proc<"generic", [FeatureXS1A]>; +def : Proc<"xs1a-generic", [FeatureXS1A]>; +def : Proc<"xs1b-generic", [FeatureXS1B]>; + +//===----------------------------------------------------------------------===// +// Declare the target which we are implementing +//===----------------------------------------------------------------------===// + +def XCore : Target { + // Pull in Instruction Info: + let InstructionSet = XCoreInstrInfo; +} |