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authorEric Christopher <echristo@apple.com>2011-06-29 17:53:29 +0000
committerEric Christopher <echristo@apple.com>2011-06-29 17:53:29 +0000
commitca42299619cf47371a42c2bda87d067e003657ea (patch)
treeb931a51acdcd1d718efdcb3d93dec46b10f057dd /lib/Target/XCore/XCoreISelLowering.h
parentd176af8cf3e3b3fb39385798e25e55449933648c (diff)
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Move XCore from getRegClassForInlineAsmConstraint to
getRegForInlineAsmConstraint. Part of rdar://9643582 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134080 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore/XCoreISelLowering.h')
-rw-r--r--lib/Target/XCore/XCoreISelLowering.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/XCore/XCoreISelLowering.h b/lib/Target/XCore/XCoreISelLowering.h
index a8d67d4ad2..9c803bef6d 100644
--- a/lib/Target/XCore/XCoreISelLowering.h
+++ b/lib/Target/XCore/XCoreISelLowering.h
@@ -148,9 +148,9 @@ namespace llvm {
SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
// Inline asm support
- std::vector<unsigned>
- getRegClassForInlineAsmConstraint(const std::string &Constraint,
- EVT VT) const;
+ std::pair<unsigned, const TargetRegisterClass*>
+ getRegForInlineAsmConstraint(const std::string &Constraint,
+ EVT VT) const;
// Expand specifics
SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;