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authorRichard Osborne <richard@xmos.com>2012-12-17 12:26:29 +0000
committerRichard Osborne <richard@xmos.com>2012-12-17 12:26:29 +0000
commitdd78daa199f653b64b997fdee46db8964e5c50cc (patch)
tree63dd4e681e921f34a0ee914d388303989c285adb /lib/Target/XCore/XCoreInstrFormats.td
parent26949489662d1f349a11809baace6b97eca0d3a2 (diff)
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Add instruction encodings / disassembly support for 0r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170322 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore/XCoreInstrFormats.td')
-rw-r--r--lib/Target/XCore/XCoreInstrFormats.td5
1 files changed, 4 insertions, 1 deletions
diff --git a/lib/Target/XCore/XCoreInstrFormats.td b/lib/Target/XCore/XCoreInstrFormats.td
index f7fa673db8..c120240d6e 100644
--- a/lib/Target/XCore/XCoreInstrFormats.td
+++ b/lib/Target/XCore/XCoreInstrFormats.td
@@ -95,8 +95,11 @@ class _F1R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{3-0} = a;
}
-class _F0R<dag outs, dag ins, string asmstr, list<dag> pattern>
+class _F0R<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<2, outs, ins, asmstr, pattern> {
+ let Inst{15-11} = opc{9-5};
+ let Inst{10-5} = 0b111111;
+ let Inst{4-0} = opc{4-0};
}
class _L4R<dag outs, dag ins, string asmstr, list<dag> pattern>