diff options
author | Robert Lytton <robert@xmos.com> | 2014-01-06 14:20:37 +0000 |
---|---|---|
committer | Robert Lytton <robert@xmos.com> | 2014-01-06 14:20:37 +0000 |
commit | e2d3dc8b817028c1724810c6e80a609cd4f888bf (patch) | |
tree | 5ef20d656338ddcc8427ed3290765c933f5afa46 /lib/Target/XCore/XCoreInstrInfo.cpp | |
parent | e452d6e547cc3de34ff8cf9e768208939d05d80a (diff) | |
download | llvm-e2d3dc8b817028c1724810c6e80a609cd4f888bf.tar.gz llvm-e2d3dc8b817028c1724810c6e80a609cd4f888bf.tar.bz2 llvm-e2d3dc8b817028c1724810c6e80a609cd4f888bf.tar.xz |
XCore target: Refactor the loading of constants into a register
This common functionality will be used to lower FRAME_TO_ARGS_OFFSET.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198610 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore/XCoreInstrInfo.cpp')
-rw-r--r-- | lib/Target/XCore/XCoreInstrInfo.cpp | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp index 33c7f31be7..33b97fba8d 100644 --- a/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/lib/Target/XCore/XCoreInstrInfo.cpp @@ -15,8 +15,11 @@ #include "XCore.h" #include "XCoreMachineFunctionInfo.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/IR/Constants.h" +#include "llvm/IR/Function.h" #include "llvm/MC/MCContext.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" @@ -399,3 +402,33 @@ ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm())); return false; } + +static inline bool isImmU6(unsigned val) { + return val < (1 << 6); +} + +static inline bool isImmU16(unsigned val) { + return val < (1 << 16); +} + +MachineBasicBlock::iterator XCoreInstrInfo::loadImmediate( + MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned Reg, uint64_t Value) const { + DebugLoc dl; + if (MI != MBB.end()) dl = MI->getDebugLoc(); + if (isMask_32(Value)) { + int N = Log2_32(Value) + 1; + return BuildMI(MBB, MI, dl, get(XCore::MKMSK_rus), Reg).addImm(N); + } + if (isImmU16(Value)) { + int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6; + return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value); + } + MachineConstantPool *ConstantPool = MBB.getParent()->getConstantPool(); + const Constant *C = ConstantInt::get( + Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Value); + unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); + return BuildMI(MBB, MI, dl, get(XCore::LDWCP_lru6), Reg) + .addConstantPoolIndex(Idx); +} |